HARDWARE ACCELERATED SYNCHRONIZATION WITH ASYNCHRONOUS TRANSACTION SUPPORT

Compact NUMA-aware Locks

Method and apparatus for monitoring a PCIe NTB

Atomic operation predictor to predict whether an atomic operation will complete successfully

SYSTEM AND METHOD FOR GENERATING PACKAGE FOR A LOW-CODE APPLICATION BUILDER

HARDWARE ACCELERATED SYNCHRONIZATION WITH ASYNCHRONOUS TRANSACTION SUPPORT

High-performance remote atomic synchronization

Compact NUMA-aware locks

CROSS-CHAIN TRANSACTION METHOD AND SYSTEM BASED ON HASH LOCKING AND SIDECHAIN TECHNOLOGY AND STORABLE MEDIUM

Processor with macro-instruction achieving zero-latency data movement

Automatic dependency configuration for managed services

COMPOSITE EVENT ESTIMATION THROUGH TEMPORAL LOGIC

LOW LATENCY AND HIGHLY PROGRAMMABLE INTERRUPT CONTROLLER UNIT

PERFORMANCE MODELING OF GRAPH PROCESSING COMPUTING ARCHITECTURES

Atomic operation predictor to predict whether an atomic operation will complete successfully

Cloud-based systems and methods for detecting and removing rootkit

Method and apparatus for secure and verifiable composite service execution and fault management on blockchain

System and method for managing multi-core accesses to shared ports

Atomicity assurance device and atomicity assurance method

Processing of plural-register-load instruction

Function as a service (FaaS) system enhancements

Compact NUMA-aware locks

Enhanced atomics for workgroup synchronization

Request of an MCS lock by guests

HARDWARE SUPPORT FOR DUAL-MEMORY ATOMIC OPERATIONS

Compact NUMA-aware locks

Verification of atomic memory operations

Index structure using atomic multiword update operations

Techniques for ordering atomic operations

LOCK-FREE ASYNCHRONOUS BUFFER

Request of an MCS lock by guests

Method and system for implementing lock free shared memory with single writer and multiple readers

Hardware access counters and event generation for coordinating multithreaded processing

Atomic memory operations on an N-way linked list

Reader-writer lock

Instructions controlling access to shared registers of a multi-threaded processor

Instructions controlling access to shared registers of a multi-threaded processor

Methods for single-owner multi-consumer work queues for repeatable tasks

Device and method for communicating between cores

Method and apparatus for conditional storing of data using a compare-and-swap based approach

Private memory regions and coherency optimization by controlling snoop traffic volume in multi-level cache hierarchy

Shiftable memory supporting atomic operation

Serializing wrapping trace buffer via a compare-and-swap instruction

Expediting RCU grace periods under user mode control

Processing engine for complex atomic operations

Contention blocking buffer

Compare and exchange operation using sleep-wakeup mechanism

LOCK-FREE FIFO

Expedited module unloading for kernel modules that execute read-copy update callback processing code

Expedited module unloading for kernel modules that execute read-copy update callback processing code

Transactional memory conflict management

Generating an ordered sequence in a database system using multiple interleaved caches

DYNAMICALLY SCALABLE PER-CPU COUNTERS

Methods for single-owner multi-consumer work queues for repeatable tasks

LOCAL-ONLY SYNCHRONIZING OPERATIONS

Structure for performing cacheline polling utilizing a store and reserve instruction

DYNAMICALLY SCALABLE PER-CPU COUNTERS

Synchronizing commands for preventing data corruption

Lock mechanism to enable atomic updates to shared memory

Fused store exclusive/memory barrier operation

Lock-free concurrent object dictionary

Atomic compare and write memory

Dynamic atomic arrays

Private memory regions and coherence optimizations

Updating shared variables atomically

Wake-and-go mechanism with exclusive system bus response

Wake-and-go mechanism with system bus response

Wake-and-go mechanism with system address bus transaction master

ALGORITHM FOR FAST LIST ALLOCATION AND FREE

Methods for single-owner multi-consumer work queues for repeatable tasks

Compare, swap and store facility with no external serialization

Using data in elements of a singly linked list without a lock in a multithreaded environment

Lock mechanism to enable atomic updates to shared memory

Multi-reader, multi-writer lock-free ring buffer

Wake-and-go mechanism with dynamic allocation in hardware private array

Wake-and-go mechanism with software save of thread state

Wake-and-go mechanism with hardware private array

Wake-and-go mechanism with data exclusivity

Optimistic semi-static transactional memory implementations

System and method for implementing hybrid single-compare-single-store operations

High performance queue implementations in multiprocessor systems

Bufferless transactional memory with runahead execution

Efficient retry for transactional memory

Address exclusive control system and address exclusive control method

Leveraging transactional memory hardware to accelerate virtualization and emulation

Structure for performing cacheline polling utilizing a store and reserve instruction

METHOD AND APPARATUS OF LOCK TRANSACTIONS PROCESSING IN SINGLE OR MULTI-CORE PROCESSOR

Wavescalar architecture having a wave order memory

System having minimum latency using timed mailbox to issue signal in advance to notify processor of the availability of the shared resources

Managing data access via a loop only if changed locking facility

Concurrent thread execution using user-level asynchronous signaling

Transactional shared memory system and method of control

BUILDING A WAVECACHE

Compare, swap and store facility with no external serialization

Atomic operation involving processors with different memory transfer operation sizes

System and method for maintaining the integrity of data transfers in shared memory configurations

Memory fence with background lock release

Building a wavecache

Implementation of load linked and store conditional operations

Concurrency technique for shared objects

Scalable method for producer and consumer elimination

Compare and exchange operation using sleep-wakeup mechanism

Information processing device, processor, processor control method, information processing device control method and cache memory

Method for monitoring a set of semaphore registers using a limited-width test bus

Wavescalar architecture having a wave order memory

RTOS/OS architecture for context switching that solves the diminishing bandwidth problem and the RTOS response time problem using unsorted ready lists

ColoredLock synchronization object, allowing flow specific policy of lock canceling

Tokenized streams for concurrent execution between asymmetric multiprocessors