191426 ⎘
Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures; Providing a specific technical effect Compatibility, e.g. with legacy hardware
Quantum Cache
#2Edge Computing Devices and Methods
#3Quantum cache
#4Quantum Information System and Method with Entanglement Tracking and Generation of Verified Quantum Information Using Metadata
#5Quantum information system and method with entanglement tracking and generation of verified quantum information using metadata
#6Quantum cache
#7Distributed quantum entanglement cache
#8MEMORY PROTOCOL WITH PROGRAMMABLE BUFFER AND CACHE SIZE
#9Backward compatibility by restriction of hardware resources
#10System and method for sharing quantum information
#11System and method for quantum cache
#12Upgrading On-Disk Format Without Service Interruption
#13Upgrading on-disk format without service interruption
#14Cost-effective deployments of a PMEM-based DMO system
#15Method for performing power management in a memory device, associated memory device and controller thereof, and associated electronic device
#16Systems and methods for adaptive access of memory namespaces
#17DIMM SSD Addressing performance techniques
#18Computing apparatus, node device, and server
#19Configuration of a physical control unit to support multiple logical control units for different tape drive types in a mainframe native tape attachment storage system
#20Short pointer mode applications in long pointer mode environments
#21Short pointer mode applications in long pointer mode environments
#22Cache coherence for processing in memory
#23Optimized read cache for persistent cache on solid state devices
#24Cache allocation with code and data prioritization
#25Storage subsystem and storage system architecture performing storage virtualization and method thereof
#26Backward compatibility by restriction of hardware resources
#27Secure migratable architecture having improved performance features
#28Secure migratable architecture having security features
#29MEMORY MANAGEMENT WITHIN SECURE MIGRATABLE ARCHITECTURE
#30Secure migratable architecture having improved performance features
#31Fork-safe memory allocation from memory-mapped files with anonymous memory behavior
#32Secure migratable architecture having high availability
#33Configuration of a physical control unit to support multiple logical control units for different tape drive types in a mainframe native tape attachment storage system
#34Fork-safe memory allocation from memory-mapped files with anonymous memory behavior
#35Managed-NAND with embedded random-access non-volatile memory
#36Memory address translation
#37Paging enablement of storage translation metadata
#38Managing data set volume table of contents
#39Garbage collection of an object
#40GARBAGE COLLECTION OF AN OBJECT
#41Memory address translation
#42System and method for pre-interleaving sequential data
#43Method for storing data as well as transponder, a read/write-device, a computer readable medium including a program element and such a program element adapted to perform this method
#44Memory address translation
#45Memory access control using redundant and non-redundant encoding
#46Solid state memory with reduced number of partially filled pages
#47Method, device and data structure for data storage on memory devices
#48Command controller, prefetch buffer and methods for accessing a serial flash in an embedded system
#49Storage subsystem and storage system architecture performing storage virtualization and method thereof
#50Storage subsystem and storage system architecture performing storage virtualization and method thereof
#51Method for processing data of flash memory by separating levels and flash memory device thereof
#52METHOD FOR ACCESSING A BIG STRUCTURE IN A 64K OPERATING ENVIRONMENT
#53Methods and devices for decompressing and executing option memory for device in shadow memory of a computer system having a BIOS
#54Efficient object pinning in a multi-threaded environment
#55Method for storing data as well as a transponder, a read/write-device, a computer readable medium including a program element and such a program element adapted to perform this method
#56CPU AND MEMORY CONNECTION ASSEMBLY TO EXTEND MEMORY ADDRESS SPACE
#57Systems and methods for writing to a memory
#58Integration of secure data transfer applications for generic IO devices
#59NAND flash module replacement for DRAM module
#60SPI bank addressing scheme for memory densities above 128Mb
#61Circuit for transforming address
#62Signal processing circuit
#63Method for accessing memory
#64Protected function calling
#65Technique for increasing control and status signal density in a fixed register address space
#66Move data facility with optional specifications
#67Efficient resource mapping beyond installed memory space by analysis of boot target
#68Command controller, prefetch buffer and methods for accessing a serial flash in an embedded system
#69Systems and methods for running a legacy 32-bit x86 virtual machine on a 64-bit x86 processor
#70Non-volatile memory with synchronous DRAM interface
#71Drive compatibility information maintenance