191437 ⎘
Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures; Providing a specific technical effect Scalability
FILE SYSTEM WITH TAGGED CAPACITY FOR MEMORY DEVICE
#2DELAYED SNOOP FOR MULTI-CACHE SYSTEMS
#3MULTICORE SHARED CACHE OPERATION ENGINE
#4CREDIT AWARE CENTRAL ARBITRATION FOR MULTI-ENDPOINT, MULTI-CORE SYSTEM
#5NAMESPACE SIZE ADJUSTMENT IN NON-VOLATILE MEMORY DEVICES
#6VIRTUAL NETWORK PRE-ARBITRATION
#7MULTICORE, MULTIBANK, FULLY CONCURRENT COHERENCE CONTROLLER
#8POOLED MEMORY ADDRESS TRANSLATION
#9SYSTEM AND METHOD FOR CACHE POOLING AND EFFICIENT USAGE AND I/O TRANSFER IN DISAGGREGATED AND MULTI-PROCESSOR ARCHITECTURES VIA PROCESSOR INTERCONNECT
#10MULTICORE SHARED CACHE OPERATION ENGINE
#11METHODS FOR EXTENDING A PROOF-OF-SPACE-TIME BLOCKCHAIN
#12CONFIGURABLE CACHE FOR COHERENT SYSTEM
#13Methods for extending a proof-of-space-time blockchain
#14PROVIDING ROLLING UPDATES OF DISTRIBUTED SYSTEMS WITH A SHARED CACHE
#15Namespace size adjustment in non-volatile memory devices
#16MULTI-PROCESSOR BRIDGE WITH CACHE ALLOCATE AWARENESS
#17Methods, devices, and systems for allocating memory space
#18DELAYED SNOOP FOR IMPROVED MULTI-PROCESS FALSE SHARING PARALLEL THREAD PERFORMANCE
#19Multicore shared cache operation engine
#20Configurable cache for coherent system
#21Pooled memory address translation
#22Virtual network pre-arbitration for deadlock avoidance and enhanced performance
#23Hinting Mechanism for Efficient Accelerator Services
#24Methods for extending a proof-of-space-time blockchain
#25Providing rolling updates of distributed systems with a shared cache
#26METHOD AND APPARATUS FOR ALLOCATING MEMORY ADDRESSES IN RESOURCE-CENTRIC NETWORKS
#27Methods for extending a proof-of-space-time blockchain
#28Custom baseboard management controller (BMC) firmware stack monitoring system and method
#29Dynamic allocation of cache based on instantaneous bandwidth consumption at computing devices
#30Adaptive credit-based replenishment threshold used for transaction arbitration in a system that supports multiple levels of credit expenditure
#31Multicore, multibank, fully concurrent coherence controller
#32CREDIT AWARE CENTRAL ARBITRATION FOR MULTI-ENDPOINT, MULTI-CORE SYSTEM
#33Namespace size adjustment in non-volatile memory devices
#34Cache optimization for graphics systems
#35DISTRIBUTED ERROR DETECTION AND CORRECTION WITH HAMMING CODE HANDOFF
#36Configurable cache for multi-endpoint heterogeneous coherent system
#37Delayed snoop for improved multi-process false sharing parallel thread performance
#38Multicore shared cache operation engine
#39Systems and methods for implementing coherent memory in a multiprocessor system
#40Methods for extending a proof-of-space-time blockchain
#41Virtual network pre-arbitration for deadlock avoidance and enhanced performance
#42Multi-processor bridge with cache allocate awareness
#43Scalable garbage collection for deduplicated storage
#44MULTICORE SHARED CACHE OPERATION ENGINE
#45Dynamic cache size management of multi-tenant caching systems
#46Dynamic allocation of cache based on instantaneous bandwidth consumption at computing devices
#47Methods for extending a proof-of-space-time blockchain
#48Cache optimization for graphics systems
#49Hardware accessible external memory
#50In-memory lightweight memory coherence protocol
#51Pooled memory address translation
#52Maintaining cache hit ratios for insertion points into a cache list to optimize memory allocation to a cache
#53Systems and methods for implementing coherent memory in a multiprocessor system
#54Namespace size adjustment in non-volatile memory devices
#55Scalable garbage collection for deduplicated storage
#56Cache optimization for graphics systems
#57Global virtual address space consistency model
#58Partitioning TLB or cache allocation
#59Flexible sizing for data buffers
#60Distributed error detection and correction with hamming code handoff
#61Multi-processor, multi-domain, multi-protocol, cache coherent, speculation aware shared memory and interconnect
#62Adaptive credit-based replenishment threshold used for transaction arbitration in a system that supports multiple levels of credit expenditure
#63Credit aware central arbitration for multi-endpoint, multi-core system
#64Multicore, multibank, fully concurrent coherence controller
#65Delayed snoop for improved multi-process false sharing parallel thread performance
#66Configurable cache for multi-endpoint heterogeneous coherent system
#67Dynamic allocation of cache based on instantaneous bandwidth consumption at computing devices
#68Prometheus: processing-in-memory heterogenous architecture design from a multi-layer network theoretic strategy
#69Unified in-memory cache
#70Coordination of cache memory operations
#71Allocation of external memory
#72Data storage system scale-out with local address remapping
#73SYSTEM AND METHOD FOR MANAGING DISTRIBUTION OF VIRTUAL MEMORY OVER MULTIPLE PHYSICAL MEMORIES
#74Method and system for operating NAND flash physical space to extend memory capacity
#75Method and apparatus for a scalable interrupt infrastructure
#76Providing rolling updates of distributed systems with a shared cache
#77Methods and memory systems for address mapping
#78Garbage collection methods and memory systems for hybrid address mapping
#79Address translation for scalable linked devices
#80Reducing concurrency of garbage collection operations
#81Namespace size adjustment in non-volatile memory devices
#82System LSI and fault detection method for system LSI
#83Apparatuses and methods for multiple address registers for a solid state device
#84Scalable display of internet content on mobile devices
#85Flexible buffer sizing in graphics processors
#86Simulator based detection of a violation of a coherency protocol in an incoherent shared memory system
#87Pooled memory address translation
#88Asymmetric coherency protocol for first and second processing circuitry having different levels of fault protection or fault detection
#89Image processing device, image processing method, and non-transitory computer readable medium for image processing
#90Systems and methods for implementing coherent memory in a multiprocessor system
#91Systems and methods for write and flush support in hybrid memory
#92Unified in-memory cache
#93Event triggered programmable prefetcher
#94Dynamic allocation of cache based on instantaneous bandwidth consumption at computing devices
#95Cache optimization for graphics systems
#96ADAPTIVE CACHE SIZING PER WORKLOAD
#97Ordered cache tiering for program build files
#98Preemptive cache management policies for processing units
#99Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slices
#100Efficiently and dynamically sized reverse map to handle variable size data
#101Locality-aware and sharing-aware cache coherence for collections of processors
#102Write filter with dynamically expandable overlay
#103Computer and control method for computer
#104Apparatus and method to improve the scalability of graphics processor unit (GPU) virtualization
#105Memory allocation on non-volatile storage
#106Multi-core processor and cache management method thereof
#107Management of external memory
#108Storage device that maintains mapping data therein
#109Reducing concurrency of garbage collection operations
#110Semiconductor package
#111Memory move instruction sequence targeting an accelerator switchboard
#112Systems and methods for maintaining the coherency of a store coalescing cache and a load cache
#113Hierarchical flash translation layer structure and method for designing the same
#114Data processing system having a coherency interconnect
#115Multiple memory rank system and selection method thereof
#116Apparatuses and methods for multiple address registers for a solid state device
#117Providing rolling updates of distributed systems with a shared cache
#118External memory for virtualization
#119Data recovery in memory devices
#120System and method for a shared cache with adaptive partitioning
#121Storage system
#122Scalable display of internet content on mobile devices
#123Fork-safe memory allocation from memory-mapped files with anonymous memory behavior
#124Private memory table for reduced memory coherence traffic
#125Private memory table for reduced memory coherence traffic
#126Burst translation look-aside buffer
#127Hierarchical cost based caching for online media
#128Pooled memory address translation
#129Fork-safe memory allocation from memory-mapped files with anonymous memory behavior
#130Computer and memory control method
#131Efficient coherency response mechanism
#132Node controller and method for responding to request based on node controller
#133Hardware apparatuses and methods to control cache line coherency
#134Provisioning of external memory
#135Dynamically provisionable and allocatable external memory
#136Heterogeneous unified memory
#137Systems and methods for expanding memory for a system on chip
#138Systems and methods for maintaining the coherency of a store coalescing cache and a load cache
#139Determining a location of a memory device in a solid state device
#140Address range transfer from first node to second node
#141Verification of management of real storage via multi-threaded thrashers in multiple address spaces
#142In-memory lightweight memory coherence protocol
#143Partition extension method and apparatus
#144Multiple memory rank system and selection method thereof
#145Electronic device
#146Scale-out non-uniform memory access
#147System and method for implementing SSD-based I/O caches
#148Lock-free, scalable read access to shared data structures using garbage collection
#149Computer system and cache control method
#150Translation layer in a solid state storage device
#151Secure memory repartitioning
#152BLOCK LEVEL STORAGE
#153Method and system for cache tiering
#154Externally programmable memory management unit
#155Memory system
#156Affinity group access to global data
#157Affinity group access to global data
#158Storage device and storage method
#159Method and system for reducing mapping table size in a storage device
#160Systems and methods for maintaining the coherency of a store coalescing cache and a load cache
#161Computer system with virtualization mechanism and management table, cache control method and computer program
#162Memory controller
#163Memory controller
#164CACHE EMPLOYING MULTIPLE PAGE REPLACEMENT ALGORITHMS
#165Method and apparatus for TLB shoot-down in a heterogeneous computing system supporting shared virtual memory
#166Reclaiming memory pages in a computing system hosting a set of virtual machines
#167Resource allocation for controller boards management functionalities in a storage management system with a plurality of controller boards, each controller board includes plurality of virtual machines with fixed local shared memory, fixed remote shared memory, and dynamic memory regions
#168Memory management system and method thereof
#169At least semi-autonomous modules in a memory system and methods
#170Memory system
#171Scalable display of internet content on mobile devices
#172Scalable display of internet content on mobile devices
#173Channel controller for multi-channel cache
#174Memory access method and information processing apparatus
#175Memory system
#176Broadcast receiving apparatus and method for managing memory thereof
#177Cache controller and control method for controlling access requests to a cache shared by plural threads that are simultaneously executed
#178Translation layer in a solid state storage device
#179Memory management system and method thereof
#180Method for providing multiple users with private access to a computer
#181Memory system and memory device
#182Nand flash memory access with relaxed timing constraints
#183Processor having a cache memory which is comprised of a plurality of large scale integration
#184Method, apparatus, and system for shared cache usage to different partitions in a socket with sub-socket partitioning
#185Allocating a global shared memory
#186Scalable display of internet content on mobile devices
#187Cache coherency within multiprocessor computer system
#188Mask usable for snoop requests
#189Technique for preserving cached information during a low power mode
#190Signal processing circuit
#191System and Method for Achieving Cache Coherency Within Multiprocessor Computer System
#192Asynchronous symmetric multiprocessing
#193SCALABLE DISPLAY OF INTERNET CONTENT ON MOBILE DEVICES
#194Method, browser client and apparatus to support full-page web browsing on hand-held devices
#195Scalable display of internet content on mobile devices
#196System having interfaces, switch, and memory bridge for CC-NUMA operation
#197Dynamic presence vector scaling in a coherency directory
#198Efficient resource mapping beyond installed memory space by analysis of boot target
#199Resolution independent display of internet content
#200Method, apparatus, and browser to support full-page web browsing on hand-held wireless devices
#201Providing cache coherency in an extended multiple processor environment
#202Tracking cache coherency in an extended multiple processor environment
#203Preemptive eviction of cache lines from a directory
#204Reducing probe traffic in multiprocessor systems
#205Scalable DMA remapping on a computer bus
#206Asynchronous symmetric multiprocessing
#207Data processing system, method and interconnect fabric that protect ownership transfer with a protection window extension
#208Method, proxy and system to support full-page web browsing on hand-held devices
#209Scalable display of internet content on mobile devices
#210Dynamic allocation of shared cache directory for optimizing performance
#211Software process migration between coherency regions without cache purges
#212Memory arrangement for tensor data