LOOKAHEAD PRIORITY COLLECTION TO SUPPORT PRIORITY ELEVATION

CMB Caching Mechanism Using Hybrid SRAM/DRAM Data Path To Store Commands

COHERENT MEMORY ACCESS

CMB CACHING USING HYBRID SRAM/DRAM DATA PATH

Coherent memory access

SENSE AMPLIFIERS AS STATIC RANDOM ACCESS MEMORY CACHE

MEMORY DEVICE WITH ON-DIE CACHE

Data storage

LOOKAHEAD PRIORITY COLLECTION TO SUPPORT PRIORITY ELEVATION

Coherent memory access

MEMORY MAPPING METHOD AND APPARATUS

Memory device with on-die cache

Lookahead priority collection to support priority elevation

Coherent memory access

Low latency dirty RAM for cache invalidation speed improvement

Coherent memory access

Cache architecture for comparing data on a single page

Intelligent prefetch disk-caching technology

Lookahead priority collection to support priority elevation

Application and processor guided memory prefetching

Interleaved cache controllers with shared metadata and related devices and systems

Memory system, memory controller for memory system, operation method of memory controller, and operation method of user device including memory device

NAND flash storage device and methods using non-NAND storage cache

Method and apparatus for reducing read/write contention to a cache

Latency by persisting data relationships in relation to corresponding data in persistent memory

MASS STORAGE CACHE IN NON VOLATILE LEVEL OF MULTI-LEVEL SYSTEM MEMORY

Systems and methods for enhancing BIOS performance by alleviating code-size limitations

Cache architecture for comparing data

INTERLEAVED CACHE CONTROLLERS WITH SHARED METADATA AND RELATED DEVICES AND SYSTEMS

Adaptive resizable cache/LCM for improved power

BLOCK CACHE STAGING IN CONTENT DELIVERY NETWORK CACHING SYSTEM

Reducing latency by persisting data relationships in relation to corresponding data in persistent memory

CONFIGURABLE CACHE ARCHITECTURE

MEMORY DEVICE AND CONTROL METHOD THEREOF

SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE

Cache memory and processor system

Aggregation of write traffic to a data store

Storage device, a host system including the storage device, and a map table updating method of the host system

A new USB protocol based computer acceleration device using multi I/O channel SLC NAND and DRAM cache

Systems and methods for dynamic optimization of flash cache in storage devices

PERFORMING CONTEXT SAVE AND RESTORE OPERATIONS IN A PROCESSOR

Writing method for solid state drive

Apparatus and method for issuing access requests to a memory controller

False power failure alert impact mitigation

Diagnostic apparatus, control unit, integrated circuit, vehicle and method of recording diagnostic data

Memory system having multiple host channel and performing a cache operation and method of operating the same

SYSTEMS AND METHODS FOR SUPPORTING A PLURALITY OF LOAD ACCESSES OF A CACHE IN A SINGLE CYCLE

Programmable address-based write-through cache control

Methods, systems, and computer readable media for providing flexible host memory buffer

Power throttle mechanism with temperature sensing and activity feedback

NVRAM caching and logging in a storage system

Methods, systems, and computer readable media for solid state drive caching across a host bus

Cache architecture for comparing data

False power failure alert impact mitigation

False power failure alert impact mitigation

Performance and power improvement on DMA writes to level two combined cache/SRAM that is cached in level one data cache and line is valid and dirty

NVRAM caching and logging in a storage system

Non-volatile memory and method with adaptive logical groups

Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain level one data cache and level two cache coherence

Aggregation of write traffic to a data store

Systems and methods for supporting a plurality of load accesses of a cache in a single cycle

Logical to physical address mapping in storage systems comprising solid state memory devices

Method to allow storage cache acceleration when the slow tier is on independent controller

System and method to buffer data

Integer and half clock step division digital variable clock divider

Managing bandwidth allocation in a processing node using distributed arbitration

Lookahead Priority Collection to Support Priority Elevation

Enhanced pipelining and multi-buffer architecture for level two cache controller to minimize hazard stalls and optimize performance

Configurable source based/requestor based error detection and correction for soft errors in multi-level cache memory to minimize CPU interrupt service routines

Priority based exception mechanism for multi-level cache controller

Programmable mapping of external requestors to privilege classes for access protection

Cache pre-allocation of ways for pipelined allocate requests

Memory attribute sharing between differing cache levels of multilevel cache

Mechanism to Update the Status of In-Flight Cache Coherence In a Multi-Level Cache Hierarchy

Programmable address-based write-through cache control

Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain level one data cache and level two cache coherence

Hazard prevention for data conflicts between level one data cache line allocates and snoop writes

Non-blocking, pipelined write allocates with allocate data merging in a multi-level cache system

Efficient cache allocation by optimizing size and order of allocate commands based on bytes required by CPU

Floating point multiplier circuit with optimized rounding calculation

Robust hamming code implementation for soft error detection, correction, and reporting in a multi-level cache system using dual banking memory scheme

Optimizing tag forwarding in a two level cache system from level one to lever two controllers for cache coherence protocol for direct memory access transfers

Efficient level two memory banking to improve performance for multiple source traffic and enable deeper pipelining of accesses by reducing bank stalls

Performance and power improvement on DMA writes to level two combined cache/SRAM that is caused in level one data cache and line is valid and dirty

Distributed user controlled multilevel block and global cache coherence with accurate completion status

Aggregation of write traffic to a data store

Dual register data path architecture with registers in a data file divided into groups and sub-groups

Cache with multiple access pipelines

Transaction info bypass for nodes coupled to an interconnect fabric

Interleaved Memory Access from Multiple Requesters

Requester based transaction status reporting in a system with multi-level memory

Closed loop adaptive voltage scaling

STORAGE APPARATUS AND CONTROL METHOD THEREOF

Aggregation of write traffic to a data store

User selectable caching management

Aggregation of write traffic to a data store

Non-volatile cache in disk drive emulation

Method of prefetching data in hard disk drive, recording medium including program to execute the method, and apparatus to perform the method

Storage apparatus and control method thereof

Data storage management method for selectively controlling reutilization of space in a virtual tape system

Information recording apparatus and control method thereof

Data storage management system and method

Memory circuit with power registers

Systems and methods for effectively interacting with a flash memory