ClassID:

191491

G06F2212/271 - CPC Classification

Classification description:

Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures; Using a specific cache architecture Non-uniform cache access [NUCA] architecture

Recent Application in this class:
#1
20240427696
2024-12-26

APPLICATION PROGRAMMING INTERFACE TO CAUSE INFORMATION TO BE READ FROM A LOCATION

#2
20240069742
2024-02-29

Chassis servicing and migration in a scale-up NUMA system

#3
20230297505
2023-09-21

STORAGE DEVICE, SYSTEM INCLUDING STORAGE DEVICE AND METHOD OPERATING STORAGE DEVICE

#4
20220050780
2022-02-17

System and method for facilitating hybrid hardware-managed and software-managed cache coherency for distributed computing

#5
20200233806
2020-07-23

Apparatus, method, and system for enhanced data prefetching based on non-uniform memory access (NUMA) characteristics

#6
20200004684
2020-01-02

Apparatus, method, and system for enhanced data prefetching based on non-uniform memory access (NUMA) characteristics

#7
20190155736
2019-05-23

Systems and methods for efficient cacheline handling based on predictions

#8
20190146693
2019-05-16

Address space access control

#9
20180190329
2018-07-05

System and method of managing data in a non-volatile memory having a staging sub-drive

#10
20180095884
2018-04-05

MASS STORAGE CACHE IN NON VOLATILE LEVEL OF MULTI-LEVEL SYSTEM MEMORY

#11
20180039576
2018-02-08

SYSTEM AND METHOD FOR A CACHE IN A MULTI-CORE PROCESSOR

#12
20180032429
2018-02-01

TECHNIQUES TO ALLOCATE REGIONS OF A MULTI-LEVEL, MULTI-TECHNOLOGY SYSTEM MEMORY TO APPROPRIATE MEMORY ACCESS INITIATORS

#13
20170357446
2017-12-14

Cache entry replacement based on availability of entries at another cache

#14
20170255553
2017-09-07

Changing cache ownership in clustered multiprocessor

#15
20170220474
2017-08-03

System and method for promoting reader groups for lock cohorting

#16
20160357683
2016-12-08

Cache memory system and processor system

#17
20160283374
2016-09-29

Changing cache ownership in clustered multiprocessor

#18
20160124854
2016-05-05

Increased bandwidth of ordered stores in a non-uniform memory subsystem

#19
20160124653
2016-05-05

Increased bandwidth of ordered stores in a non-uniform memory subsystem

#20
20160041906
2016-02-11

Sharding of in-memory objects across NUMA nodes

#21
20160019150
2016-01-21

Information processing device, control method of information processing device and control program of information processing device

#22
20160004639
2016-01-07

System and method for a cache in a multi-core processor

#23
20150278091
2015-10-01

Method and apparatus for implementing a heterogeneous memory subsystem

#24
20150212940
2015-07-30

Identifying performance limiting internode data sharing on NUMA platforms

#25
20150193344
2015-07-09

Data shuffling in a non-uniform memory access device

#26
20150113230
2015-04-23

DIRECTORY STORAGE METHOD AND QUERY METHOD, AND NODE CONTROLLER

#27
20140006713
2014-01-02

Cache collaboration in tiled processor systems

#28
20130275676
2013-10-17

Tiled storage array with systolic move-to-front organization

#29
20130179641
2013-07-11

Memory system including a spiral cache

#30
20120324166
2012-12-20

Computer-implemented method of processing resource management

#31
20120311265
2012-12-06

Read and write aware cache with a read portion and a write portion of a tag and status array

#32
20120179872
2012-07-12

Global instructions for spiral cache management

#33
20120137075
2012-05-31

System and method for a cache in a multi-core processor

#34
20110153951
2011-06-23

Global instructions for spiral cache management

#35
20110145545
2011-06-16

Computer program product for managing processing resources

#36
20110072214
2011-03-24

Read and write aware cache storing cache lines in a read-often portion and a write-often portion

#37
20110022754
2011-01-27

BUS ENHANCED NETWORK ON CHIP

#38
20100332761
2010-12-30

Reconfigurable cache

#39
20100299482
2010-11-25

Method and apparatus for determining cache storage locations based on latency requirements

#40
20100122100
2010-05-13

Tiled memory power management

#41
20100122057
2010-05-13

Tiled storage array with systolic move-to-front reorganization

#42
20100122035
2010-05-13

Spiral cache memory and method of operating a spiral cache

#43
20100122034
2010-05-13

Storage array tile supporting systolic movement operations

#44
20100122033
2010-05-13

Memory system including a spiral cache

#45
20100122031
2010-05-13

Spiral cache power management, adaptive sizing and interface operations

#46
20100115204
2010-05-06

Non-uniform cache architecture (NUCA)

#47
20090254712
2009-10-08

ADAPTIVE CACHE ORGANIZATION FOR CHIP MULTIPROCESSORS

#48
20090235030
2009-09-17

Cache system including a plurality of processing units

#49
20090178052
2009-07-09

Latency-aware thread scheduling in non-uniform cache architecture systems

#50
20080313407
2008-12-18

LATENCY-AWARE REPLACEMENT SYSTEM AND METHOD FOR CACHE MEMORIES

#51
20080313404
2008-12-18

Multiprocessor system and operating method of multiprocessor system

#52
20070136531
2007-06-14

Credit mechanism for multiple banks of shared cache

#53
20070083783
2007-04-12

Reducing power consumption at a cache

#54
20070033423
2007-02-08

Reducing power consumption at a cache

#55
20060248287
2006-11-02

Methods and arrangements for reducing latency and snooping cost in non-uniform cache memory architectures

#56
20060143384
2006-06-29

System and method for non-uniform cache in a multi-core processor

#57
20060112228
2006-05-25

Cache line placement prediction for multiprocessor non-uniform cache architecture systems

#58
20060080506
2006-04-13

Data replication in multiprocessor NUCA systems to reduce horizontal cache thrashing

#59
20060075192
2006-04-06

Dynamic reconfiguration of cache memory

#60
20060041720
2006-02-23

Latency-aware replacement system and method for cache memories

#61
20050132140
2005-06-16

Non-uniform cache apparatus, systems, and methods

#62
20050114618
2005-05-26

Systolic memory arrays