191491 ⎘
Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures; Using a specific cache architecture Non-uniform cache access [NUCA] architecture
APPLICATION PROGRAMMING INTERFACE TO CAUSE INFORMATION TO BE READ FROM A LOCATION
#2Chassis servicing and migration in a scale-up NUMA system
#3STORAGE DEVICE, SYSTEM INCLUDING STORAGE DEVICE AND METHOD OPERATING STORAGE DEVICE
#4System and method for facilitating hybrid hardware-managed and software-managed cache coherency for distributed computing
#5Apparatus, method, and system for enhanced data prefetching based on non-uniform memory access (NUMA) characteristics
#6Apparatus, method, and system for enhanced data prefetching based on non-uniform memory access (NUMA) characteristics
#7Systems and methods for efficient cacheline handling based on predictions
#8Address space access control
#9System and method of managing data in a non-volatile memory having a staging sub-drive
#10MASS STORAGE CACHE IN NON VOLATILE LEVEL OF MULTI-LEVEL SYSTEM MEMORY
#11SYSTEM AND METHOD FOR A CACHE IN A MULTI-CORE PROCESSOR
#12TECHNIQUES TO ALLOCATE REGIONS OF A MULTI-LEVEL, MULTI-TECHNOLOGY SYSTEM MEMORY TO APPROPRIATE MEMORY ACCESS INITIATORS
#13Cache entry replacement based on availability of entries at another cache
#14Changing cache ownership in clustered multiprocessor
#15System and method for promoting reader groups for lock cohorting
#16Cache memory system and processor system
#17Changing cache ownership in clustered multiprocessor
#18Increased bandwidth of ordered stores in a non-uniform memory subsystem
#19Increased bandwidth of ordered stores in a non-uniform memory subsystem
#20Sharding of in-memory objects across NUMA nodes
#21Information processing device, control method of information processing device and control program of information processing device
#22System and method for a cache in a multi-core processor
#23Method and apparatus for implementing a heterogeneous memory subsystem
#24Identifying performance limiting internode data sharing on NUMA platforms
#25Data shuffling in a non-uniform memory access device
#26DIRECTORY STORAGE METHOD AND QUERY METHOD, AND NODE CONTROLLER
#27Cache collaboration in tiled processor systems
#28Tiled storage array with systolic move-to-front organization
#29Memory system including a spiral cache
#30Computer-implemented method of processing resource management
#31Read and write aware cache with a read portion and a write portion of a tag and status array
#32Global instructions for spiral cache management
#33System and method for a cache in a multi-core processor
#34Global instructions for spiral cache management
#35Computer program product for managing processing resources
#36Read and write aware cache storing cache lines in a read-often portion and a write-often portion
#37BUS ENHANCED NETWORK ON CHIP
#38Reconfigurable cache
#39Method and apparatus for determining cache storage locations based on latency requirements
#40Tiled memory power management
#41Tiled storage array with systolic move-to-front reorganization
#42Spiral cache memory and method of operating a spiral cache
#43Storage array tile supporting systolic movement operations
#44Memory system including a spiral cache
#45Spiral cache power management, adaptive sizing and interface operations
#46Non-uniform cache architecture (NUCA)
#47ADAPTIVE CACHE ORGANIZATION FOR CHIP MULTIPROCESSORS
#48Cache system including a plurality of processing units
#49Latency-aware thread scheduling in non-uniform cache architecture systems
#50LATENCY-AWARE REPLACEMENT SYSTEM AND METHOD FOR CACHE MEMORIES
#51Multiprocessor system and operating method of multiprocessor system
#52Credit mechanism for multiple banks of shared cache
#53Reducing power consumption at a cache
#54Reducing power consumption at a cache
#55Methods and arrangements for reducing latency and snooping cost in non-uniform cache memory architectures
#56System and method for non-uniform cache in a multi-core processor
#57Cache line placement prediction for multiprocessor non-uniform cache architecture systems
#58Data replication in multiprocessor NUCA systems to reduce horizontal cache thrashing
#59Dynamic reconfiguration of cache memory
#60Latency-aware replacement system and method for cache memories
#61Non-uniform cache apparatus, systems, and methods
#62Systolic memory arrays