191501 ⎘
Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures; Providing cache or TLB in specific location of a processing system In special purpose processing node, e.g. vector processor
VICTIM CACHE THAT SUPPORTS DRAINING WRITE-MISS ENTRIES
#2WRITE MERGING ON STORES WITH DIFFERENT TAGS
#3METHODS AND APPARATUS TO FACILITATE WRITE MISS CACHING IN CACHE SYSTEM
#4METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A COHERENT VICTIM CACHE WITH PARALLEL DATA PATHS
#5WRITE MERGING ON STORES WITH DIFFERENT PRIVILEGE LEVELS
#6METHODS AND APPARATUS TO FACILITATE ATOMIC OPERATIONS IN VICTIM CACHE
#7VICTIM CACHE WITH WRITE MISS MERGING
#8HYBRID VICTIM CACHE AND WRITE MISS BUFFER WITH FENCE OPERATION
#9METHODS AND APPARATUS FOR MULTI-BANKED VICTIM CACHE WITH DUAL DATAPATH
#10AGGRESSIVE WRITE FLUSH SCHEME FOR A VICTIM CACHE
#11METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM
#12ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM
#13FULLY PIPELINED READ-MODIFY-WRITE SUPPORT
#14METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRITE MERGING
#15METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED DATA RAM CACHE FOR BANK ARBITRATION
#16METHOD FOR STORING AND ACCESSING A DATA OPERAND IN A MEMORY UNIT
#17VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES
#18ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE
#19METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SYSTEM
#20METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A VICTIM CACHE
#21Victim cache with write miss merging
#22VICTIM CACHE THAT SUPPORTS DRAINING WRITE-MISS ENTRIES
#23PREFETCH KILL AND REVIVAL IN AN INSTRUCTION CACHE
#24METHODS AND APPARATUS TO REDUCE READ-MODIFY-WRITE CYCLES FOR NON-ALIGNED WRITES
#25Methods and apparatus to facilitate atomic operations in victim cache
#26Methods and apparatus for allocation in a victim cache system
#27Hybrid victim cache and write miss buffer with fence operation
#28Methods and apparatus for eviction in dual datapath victim cache system
#29Write merging on stores with different privilege levels
#30Atomic compare and swap in a coherent cache system
#31Methods and apparatus to reduce bank pressure using aggressive write merging
#32WRITE MERGING ON STORES WITH DIFFERENT TAGS
#33Fully pipelined read-modify-write support
#34Victim cache that supports draining write-miss entries
#35METHODS AND APPARATUS TO FACILITATE WRITE MISS CACHING IN CACHE SYSTEM
#36Methods and apparatus to facilitate read-modify-write support in a victim cache
#37Prefetch kill and revival in an instruction cache
#38METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A COHERENT VICTIM CACHE WITH PARALLEL DATA PATHS
#39Atomic operations and histogram operations in a cache pipeline
#40Hardware interconnect with memory coherence
#41Methods and apparatus for allocation in a victim cache system
#42MEMORY SYSTEM FOR ACCELERATING GRAPH NEURAL NETWORK PROCESSING
#43Aggressive write flush scheme for a victim cache
#44Methods and apparatus to facilitate atomic operations in victim cache
#45Write merging on stores with different privilege levels
#46Victim cache with write miss merging
#47Write merging on stores with different tags
#48Prefetch kill and revival in an instruction cache
#49Methods and apparatus for multi-banked victim cache with dual datapath
#50Methods and apparatus to facilitate atomic compare and swap in cache for a coherent level 1 data cache system
#51Victim cache that supports draining write-miss entries
#52Victim cache with write miss merging
#53Victim cache with dynamic allocation of entries
#54Aggressive write flush scheme for a victim cache
#55Methods and apparatus for allocation in a victim cache system
#56Methods and apparatus to facilitate read-modify-write support in a victim cache
#57Methods and apparatus to facilitate atomic operations in victim cache
#58Methods and apparatus for inflight data forwarding and invalidation of pending writes in store queue
#59Methods and apparatus for eviction in dual datapath victim cache system
#60Methods and apparatus to reduce read-modify-write cycles for non-aligned writes
#61Methods and apparatus to facilitate fully pipelined read-modify-write support in level 1 data cache using store queue and data forwarding
#62Methods and apparatus for read-modify-write support in multi-banked data RAM cache for bank arbitration
#63Methods and apparatus to facilitate write miss caching in cache system
#64Write merging on stores with different privilege levels
#65Methods and apparatus to reduce bank pressure using aggressive write merging
#66Write merging on stores with different tags
#67Methods and apparatus to facilitate an atomic operation and/or a histogram operation in cache pipeline
#68Hybrid victim cache and write miss buffer with fence operation
#69Methods and apparatus to facilitate read-modify-write support in a coherent victim cache with parallel data paths
#70MECHANISM FOR ISSUING REQUESTS TO AN ACCELERATOR FROM MULTIPLE THREADS
#71Managing low-level instructions and core interactions in multi-core processors
#72Prefetch kill and revival in an instruction cache
#73Dynamic acceleration of data processor operations using data-flow analysis
#74CACHE BEHAVIOR FOR SECURE MEMORY REPARTITIONING SYSTEMS
#75APPARATUS AND METHOD INCLUDING A THERMAL NOISE ADAPTIVE SCHEDULER FOR CONTROLLING A QUANTUM COMPUTER
#76PROCESSING SCATTERED DATA USING AN ADDRESS BUFFER
#77Microcontroller for memory management unit
#78System and method for using persistent memory to accelerate write performance
#79Replaying memory transactions while resolving memory access faults
#80Efficient address translation caching in a processor that supports a large number of different address spaces
#81Arithmetic processing device, information processing device, and control method of arithmetic processing device
#82Multi-granular cache coherence
#83Cache replacement policy
#84Power reduction for fully associated translation lookaside buffer (TLB) and content addressable memory (CAM)
#85Lookahead scheme for prioritized reads
#86Arithmetic processing device, arithmetic processing system, and method for controlling arithmetic processing device
#87Controlling a dynamically instantiated cache
#88Microcontroller for memory management unit
#89Opportunistic migration of memory pages in a unified virtual memory system
#90Replaying memory transactions while resolving memory access faults
#91Flush control apparatus, flush control method and cache memory apparatus
#92Translation management instructions for updating address translation data structures in remote processing nodes
#93Translation management instructions for updating address translation data structures in remote processing nodes
#94Lookahead scheme for prioritized reads
#95Intelligence for controlling virtual storage appliance storage allocation
#96Systems, methods, and devices for cache block coherence
#97Tracking written addresses of a shared memory of a multi-core processor
#98Channel controller for multi-channel cache
#99Configurable cache for multiple clients
#100Processor with coprocessor interfacing functional unit for forwarding result from coprocessor to retirement unit
#101Prefetch kill and revival in an instruction cache