191508 ⎘
Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures; Providing cache or TLB in specific location of a processing system In system interconnect, e.g. between two buses
PRE-FETCHING ADDRESS TRANSLATION FOR COMPUTATION OFFLOADING
#2SYSTEMS AND METHODS FOR TRANSFORMING DATA IN-LINE WITH READS AND WRITES TO COHERENT HOST-MANAGED DEVICE MEMORY
#3Identification of a computing device accessing a shared memory
#4Memory descriptor list caching and pipeline processing
#5Identification of a computing device accessing a shared memory
#6Identification of a computing device accessing a shared memory
#7Memory descriptor list caching and pipeline processing
#8Memory system and SoC including linear remapper and access window
#9Identification of a computing device accessing a shared memory
#10Identification of a computing device accessing a shared memory
#11Method and apparatus for copying data using cache
#12Parallel, pipelined, integrated-circuit implementation of a computational engine
#13Method and apparatus for performing dynamic configuration
#14System on chip including memory management unit and memory address translation method thereof
#15Methods and arrangements for hybrid data storage
#16Device with cache command forwarding
#17Monitor implementation in a multicore processor with inclusive LLC
#18Enforcing global ordering using an inter-queue ordering mechanism
#19Selectively prefetch method and bridge module
#20Microprocessor and method for utilizing disparity between bus clock and core clock frequencies to prioritize cache line fill bus access requests
#21Intelligent hierarchical caching based on metrics for objects in different cache levels
#22Translation lookaside buffer (TLB) clustering system for checking multiple memory address translation entries each mapping a viritual address offset