191537 ⎘
Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures; Details of cache memory; Reconfiguration of cache memory of operating mode, e.g. cache mode or local memory mode
SYSTEMS AND METHODS FOR ADAPTIVE CACHE CONFIGURATION
#2SYSTEMS AND METHODS FOR A CROSS-LAYER KEY-VALUE STORE WITH A COMPUTATIONAL STORAGE DEVICE
#3Cache block budgeting techniques
#4Cache block budgeting techniques
#5Instance deployment method, instance management node, computing node, and computing device
#6TREATING MAIN MEMORY AS A COLLECTION OF TAGGED CACHE LINES FOR TRACE LOGGING
#7Utilization of a distributed index to provide object memory fabric coherency
#8Adaptive caching in a multi-tier cache
#9Method and apparatus for adjusting cache prefetch policies based on predicted cache pollution from dynamically evolving workloads
#10Memory system with program mode switching based on mixed and sequential workloads
#11Distributed index for fault tolerant object memory fabric
#12Method for managing a cache memory of an electronic processor
#13Cache and method for managing cache
#14Memory having a static cache and a dynamic cache
#15Method, apparatus, and computer program product for providing cache service
#16Utilization of a distributed index to provide object memory fabric coherency
#17Cache partitioning in a multicore processor
#18Memory having a static cache and a dynamic cache
#19Memory utilized as both system memory and near memory
#20Fast cache warm-up
#21Memory having a static cache and a dynamic cache
#22Write-back cache for storage controller using persistent system memory
#23Distributed index for fault tolerant object memory fabric
#24Utilization of a distributed index to provide object memory fabric coherency
#25Multi-core processor and operation method thereof
#26Dynamic management of expandable cache storage for multiple network shares configured in a file server
#27System and method for dynamic optimization for burst and sustained performance in solid state drives
#28Cache partitioning in a multicore processor
#29CONFIGURABLE CACHE ARCHITECTURE
#30Memory having a static cache and a dynamic cache
#31Reconfigurable fetch pipeline
#32Fusible and reconfigurable cache architecture
#33Memory system
#34Method for dynamically establishing translation layer of solid state disk
#35Utilization of a distributed index to provide object memory fabric coherency
#36System and method for adaptive implementation of victim cache mode in a portable computing device
#37Implementation of an object memory centric cloud
#38Managing meta-data in an object memory fabric
#39Distributed index for fault tolerant object memory fabric
#40Distributed caching systems and methods
#41Content-addressable memory device
#42Configuring wearable devices
#43Reconfigurable fetch pipeline
#44Active memory processor system
#45Data storage system with passive partitioning in a secondary memory
#46Cache partitioning in a multicore processor
#47Active memory processor system
#48Method and apparatus for managing write back cache
#49Flexible utilization of block storage in a computing system
#50Memory management apparatus, method, and system
#51Dynamically partition a volatile memory for a cache and a memory partition
#52Cache with scratch pad memory structure and processor including the cache
#53Multi-core system and external input/output bus control method
#54Expandable data cache
#55Mechanisms and techniques for providing cache tags in dynamic random access memory
#56Polymorphic Stacked DRAM Memory Architecture
#57INFORMATION PROCESSING DEVICE
#58Multi-core active memory processor system
#59Active memory processor system
#60Storage apparatus and method for shredding storage medium
#61DATA STORAGE APPARATUS AND CONTROLLING METHOD OF THE DATA STORAGE APPARATUS
#62Configurable cache for multiple clients
#63Optical disc drive device
#64System on chip and electronic system having the same
#65Storage controller and firmware updating method
#66Method of converting a hybrid hard disk drive to a normal HDD
#67Methods For Supporting Readydrive And Readyboost Accelerators In A Single Flash-Memory Storage Device
#68Systems For Supporting Readydrive And Readyboost Accelerators In A Single Flash-Memory Storage Device
#69Inter-processor communication method using a shared cache memory in a storage system
#70Method and apparatus for managing write back cache
#71Local scratchpad and data caching system
#72Multi-core debugger
#73Method and related system of dynamic compiler resolution
#74Method and system of adaptive dynamic compiler resolution
#75Method and apparatus for code optimization
#76Method and system of control flow graph construction
#77Method and system for thread abstraction
#78Method and system for implementing an interrupt handler
#79Method and system for implementing interrupt service routines
#80Method and system for managing virtual memory
#81Removing local RAM size limitations when executing software code
#82Delegating tasks between multiple processor cores
#83Identifying code for compilation
#84Method and system to construct a data-flow analyzer for a bytecode verifier
#85Modifying an instruction stream using one or more bits to replace an instruction or to replace an instruction and to subsequently execute the replaced instruction
#86Method and system for processing a “WIDE” opcode when it is not used as a prefix for an immediately following opcode
#87Method and system to disable the "wide" prefix
#88Automatic operand load, modify and store
#89Unpack instruction
#90Pack instruction
#91Memory access instruction with optional error check
#92Compare instruction
#93Optimizing data manipulation in media processing applications
#94Splitting execution of a floating-point add instruction between an integer pipeline for performing mantissa addition and a hardware state machine
#95Method and system of informing a micro-sequence of operand width
#96Method and system for obtaining an immediate operand of a bytecode for use by a micro-sequence
#97Storing contexts for thread switching
#98Method and system for accessing indirect memories
#99Context save and restore with a stack-based memory structure
#100Cache memory usable as scratch pad storage
#101Memory usable in cache mode or scratch pad mode to reduce the frequency of memory accesses
#102Interrupt management in dual core processors
#103Emulating a direct memory access controller
#104Method and system for multiple object representation
#105Method and system for shared object data member zones
#106Method and system provide concurrent access to a software object
#107Method and system for making a java system call
#108Method and system to emulate an M-bit instruction set
#109Method and system for dynamic address translation
#110Method, system, and apparatus for explicit control over a disk cache memory