191555 ⎘
Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures; Details of virtual memory and virtual address translation Page size control
MEMORY RECLAIMING METHOD AND ELECTRONIC DEVICE
#2MEMORY ARRAY PAGE TABLE WALK
#3PREFETCH MANAGEMENT FOR MEMORY
#4PREFETCH MANAGEMENT FOR MEMORY
#5Memory array page table walk
#6Virtual Memory Management
#7Address translation cache and system including the same
#8Technologies for execute only transactional memory
#9VIRTUAL MEMORY WITH DYNAMIC SEGMENTATION FOR MULTI-TENANT FPGAS
#10Memory array page table walk
#11Determining page size via page table cache
#12METHOD, SYSTEM, AND APPARATUS FOR PAGE SIZING EXTENSION
#13Virtual memory management
#14Prefetch management for memory
#15Host-based acceleration of a content addressable storage system
#16Memory system, memory controller and method for operating memory controller
#17Methods and apparatuses for managing page cache in virtualization service
#18METHOD, SYSTEM, AND APPARATUS FOR PAGE SIZING EXTENSION
#19Methods and systems for predicting virtual address
#20Technologies for execute only transactional memory
#21Virtual memory management
#22Memory array page table walk
#23Prefetching data based on data transfer within a memory system
#24Prefetch management for memory
#25System and method for detection of underprovisioning of memory in virtual machines
#26Decoupling memory metadata granularity from page size
#27Address space resizing table for simulation of processing of target program code on a target data processing apparatus
#28Attribute driven memory allocation
#29Mechanism to support variable size page translations
#30Creating a dynamic address translation with translation exception qualifiers
#31Hardware-based pre-page walk virtual address transformation independent of page size utilizing bit shifting based on page size
#32Method of processing data based on erase operations of logical pages related to data compression rate of mapping table in data storage device
#33Secure management of operations on protected virtual machines
#34Compressed pages having data and compression metadata
#35Intelligently partitioning data cache to allocate space for translation entries
#36Apparatus and method for efficient utilisation of an address translation cache
#37Range-based memory system
#38Key-value based message oriented middleware
#39Logging changes to data stored in distributed data storage system
#40Hybrid key-value store
#41Shared filesystem for distributed data storage system
#42Caching the topology of a distributed data storage system
#43Page list based crash recovery
#44Key value based block device
#45Page based data persistency
#46Memory management supporting huge pages
#47Page table management for differing virtual and physical address page alignment
#48Memory array page table walk
#49Variable translation-lookaside buffer (TLB) indexing
#50Configurable skewed associativity in a translation lookaside buffer
#51Electronic device and page merging method therefor
#52Memory structure comprising scratchpad memory
#53Translation lookaside buffer
#54Memory management supporting huge pages
#55Creating a dynamic address translation with translation exception qualifiers
#56Systems and methods for accessing a unified translation lookaside buffer
#57Creating a dynamic address translation with translation exception qualifiers
#58Virtual machine based huge page balloon support
#59VIRTUAL COMPUTER SYSTEM CONTROL METHOD AND VIRTUAL COMPUTER SYSTEM
#60Method, system, and apparatus for page sizing extension
#61Method, system, and apparatus for page sizing extension
#62Translating access requests for a multi-level page data structure
#63Supporting invalidation commands for non-volatile memory
#64Memory device with page emulation mode
#65Virtual machine based huge page balloon support
#66Systems and methods for accessing a unified translation lookaside buffer
#67Integrated systems and methods for the transactional management of main memory and data storage
#68Secure management of operations on protected virtual machines
#69Migrating pages of different sizes between heterogeneous processors
#70Translation lookaside buffer
#71Burst translation look-aside buffer
#72DATA STORAGE DEVICE SUPPORTING ACCELERATED DATABASE OPERATIONS
#73APPLICATION-LAYER MANAGED MEMORY CACHE
#74Verification of management of real storage via multi-threaded thrashers in multiple address spaces
#75MEMORY SYSTEM AND METHOD FOR CONTROLLING SAME
#76Memory management for graphics processing unit workloads
#77Efficient key collision handling
#78Memory system and controller
#79Flash storage devices and methods for organizing address mapping tables in flash storage devices
#80Identification of low-activity large memory pages
#81Identification of low-activity large memory pages
#82Verification of management of real storage via multi-threaded thrashers in multiple address spaces
#83Creating A Dynamic Address Translation With Translation Exception Qualifiers
#84Secure transport of encrypted virtual machines with continuous owner access
#85Out-of-place presetting based on indirection table
#86Systems and methods for accessing a unified translation lookaside buffer
#87Managing translation of a same address across multiple contexts using a same entry in a translation lookaside buffer
#88Managing translation of a same address across multiple contexts using a same entry in a translation lookaside buffer
#89System, method and computer-readable medium for dynamically mapping a non-volatile memory store
#90SYSTEM AND METHOD FOR RESOLVING DRAM PAGE CONFLICTS BASED ON MEMORY ACCESS PATTERNS
#91MICRO-JOURNALING FOR FILE SYSTEM BASED ON NON-VOLATILE MEMORY
#92Hypervisor managing memory addressed above four gigabytes
#93Virtual machine migration with swap pages
#94Virtual machine migration with swap pages
#95Method and apparatus for reformatting page table entries for cache storage
#96Storage system and writing method thereof
#97Memory device with page emulation mode
#98System and method to prioritize large memory page allocation in virtualized systems
#99Variable page sizing for improved physical clustering
#100Hardware-based pre-page walk virtual address transformation where the virtual address is shifted by current page size and a minimum page size
#101Migrating pages of different sizes between heterogeneous processors
#102Reserving fixed page areas in real storage increments
#103Overlap checking for a translation lookaside buffer (TLB)
#104Flexible page sizes for virtual memory
#105Techniques for utilizing translation lookaside buffer entry numbers to improve processor performance
#106Intelligent far memory bandwith scaling
#107MANAGING BACKING OF VIRTUAL MEMORY
#108Load page table entry address instruction execution based on an address translation format control field
#109Identification and consolidation of page table entries
#110Page table entry consolidation
#111Identification and consolidation of page table entries
#112Page table entry consolidation
#113Shared memory access using independent memory maps
#114Memory range preferred sizes and out-of-bounds counts
#115Multiple page size memory management unit
#116Systems and methods for accessing a unified translation lookaside buffer
#117Sub page and page memory management apparatus and method
#118Method, system, and apparatus for page sizing extension
#119Address translation device, processing device and control method of processing device
#120Optimizing TLB entries for mixed page size storage in contiguous memory
#121Large-page optimization in virtual memory paging systems
#122Variable page sizing for improved physical clustering
#123VIRTUAL-MEMORY SYSTEM WITH VARIABLE-SIZED PAGES
#124Semiconductor memory device
#125Method of memory management for server-side scripting language runtime system
#126System and method to prioritize large memory page allocation in virtualized systems
#127ADDRESS CONVERSION APPARATUS
#128Dynamic address translation with translation exception qualifier
#129Translation lookaside buffer
#130Management of low-paging space conditions in an operating system
#131Application run-time memory optimizer
#132Recording dirty information in software distributed shared memory systems
#133Load page table entry address instruction execution based on an address translation format control field
#134High performance cache translation look-aside buffer (TLB) lookups using multiple page size prediction
#135Multiple page size segment encoding
#136Efficient support of multiple page size segments
#137Optimizing TLB entries for mixed page size storage in contiguous memory
#138Software assisted translation lookaside buffer search mechanism
#139Delayed replacement of cache entries
#140Method and system to accelerate address translation
#141Preventing duplicate entries in a non-blocking TLB structure that supports multiple page sizes
#142Processing system implementing variable page size memory organization using a multiple page per entry translation lookaside buffer
#143Efficient memory translator with variable size cache line coverage
#144Extended page size using aggregated small pages
#145AUTOMATICALLY USING SUPERPAGES FOR STACK MEMORY ALLOCATION
#146Large memory pages for shared libraries
#147SEMICONDUCTOR INTEGRATED CIRCUIT, INFORMATION PROCESSING DEVICE, AND CONTROL METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT
#148Apparatus and method to translate virtual addresses to physical addresses in a base plus offset addressing mode
#149Method and apparatus for inclusion of TLB entries in a micro-op cache of a processor
#150Calculator and TLB control method
#151Pretranslating Input/Output Buffers In Environments With Multiple Page Sizes
#152Opportunistic page largification
#153Direct memory access (DMA) address translation in an input/output memory management unit (IOMMU)
#154Virtual memory management
#155Translation of virtual to physical addresses
#156Method of memory management for server-side scripting language runtime system
#157Dynamic address translation with translation exception qualifier
#158Dynamic address translation with DAT protection
#159Large-page optimization in virtual memory paging systems
#160Load page table entry address instruction execution based on an address translation format control field
#161Dynamic address translation with format control
#162Method, system, and apparatus for page sizing extension
#163Translation look-aside buffer with variable page sizes
#164Processing system implementing variable page size memory organization using a multiple page per entry translation lookaside buffer
#165Processing system implementing multiple page size memory organization with multiple translation lookaside buffers having differing characteristics
#166Processing system implementing variable page size memory organization
#167Method and apparatus for dynamically adjusting page size in a virtual memory range
#168Pretranslating input/output buffers in environments with multiple page sizes
#169Method and apparatus for faster execution path
#170Prefetching in a virtual memory system based upon repeated accesses across page boundaries
#171Prefetching in a virtual memory system based upon repeated accesses across page boundaries
#172Page replacement policy for systems having multiple page sizes
#173Page replacement policy for systems having multiple page sizes
#174GUARD BANDS IN VERY LARGE VIRTUAL MEMORY PAGES
#175Techniques to manage media files
#176Hybrid techniques for memory virtualization in a computer system
#177Data processor and IP module for data processor
#178Multiple page size address translation incorporating page size prediction
#179Method and system for predicting the performance benefits of mapping subsets of application data to multiple page sizes
#180Address translation for input/output (I/O) devices and interrupt remapping for I/O devices in an I/O memory management unit (IOMMU)
#181High speed CAM lookup using stored encoded key
#182Memory management
#183Virtual memory fragment aware cache
#184Scalable partition memory mapping system
#185Efficient algorithm for multiple page size support in IPF long format VHPT
#186Memory management in a multiprocessor system
#187Statement regarding federally sponsored-research or development
#188Systems and methods for identifying and registering a range of virtual memory
#189Method and mechanism for efficiently creating large virtual memory pages in a multiple page size environment
#190Microprocessor including a configurable translation lookaside buffer
#191Page replacement policy for systems having multiple page sizes
#192System and method of large page handling in a virtual memory system
#193Method and apparatus for fragment processing in a virtual memory system
#194Method and system for optimizing translation lookaside buffer entries
#195Method and system for a second level address translation in a virtual machine environment
#196Method and apparatus for selecting operating characteristics of a content addressable memory by using a compare mask
#197Multiple page size address translation incorporating page size prediction
#198Method and apparatus for protecting TLB's VPN from soft errors
#199Methods and apparatus for address translation from an external device to a memory of a processor
#200System and method for information handling system memory page mapping optimization
#201Serially indexing a cache memory
#202Pretranslating input/output buffers in environments with multiple page sizes
#203Method of determining whether a virtual address corresponds to a physical address in a translation lookaside buffer
#204Apparatus to map virtual pages to disparate-sized, non-contiguous real pages
#205Demotion of memory pages to largest possible sizes
#206Method and apparatus for performing address translation in a computer system
#207Method of efficiently handling multiple page sizes in an effective to real address translation (ERAT) table
#208MicroTLB and micro tag for reducing power in a processor
#209Data processor and IP module for data processor
#210System and method for encoding page size information
#211Address translation using a page size tag
#212Accessing in parallel stored data for address translation
#213Mini-translation lookaside buffer for use in memory translation
#214Fine-grained access memory controller
#215Multiple page-size translation lookaside buffer
#216Multiple page-size translation lookaside buffer
#217Managing multi-granularity flash translation layers in solid state drives
#218Multiple page-size translation lookaside buffer
#219Apparatus, system and method for memory management