191558 ⎘
Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures; Details of virtual memory and virtual address translation Same page detection
MEMORY CONTROLLER AND RELATED METHODS FOR IMPLEMENTING AN ADDRESS-BASED DYNAMIC PAGE CLOSE POLICY
#2HOST PERFORMANCE BOOSTER L2P HANDOFF
#3Indexless logical-to-physical translation table
#4Prefetching data to reduce cache misses
#5Process isolation for out of process page fault handling
#6Apparatus and method for handling access requests
#7Process isolation for out of process page fault handling
#8Filtering of redundantly scheduled write passes
#9Pseudo-invalidating dynamic address translation (DAT) tables of a DAT structure associated with a workload
#10Real time memory address translation device
#11Apparatus and method for performing cache maintenance over a virtual page
#12Multi-threaded translation and transaction re-ordering for memory management units
#13Virtual memory mapping for improved DRAM page locality
#14Method of controlling memory swap operation and data processing system using same
#15Systems and methods for reducing first level cache energy by eliminating cache address tags
#16Stride prefetching across memory pages
#17Speculative addressing using a virtual address-to-physical address page crossing buffer
#18Page crossing prefetches
#19Concurrent page table walker control for TLB miss handling
#20Performing memory accesses while omitting unnecessary address translations
#21Apparatuses, Systems, and Methods for Reducing Translation Lookaside Buffer (TLB) Lookups
#22Program trace message generation for page crossing events for debug
#23Performing memory accesses while omitting unnecessary address translations
#24Dynamic translation in the presence of intermixed code and data
#25Apparatus and method to translate virtual addresses to physical addresses in a base plus offset addressing mode
#26Jump starting prefetch streams across page boundaries
#27Address translation method and apparatus
#28Collapsible front-end translation for instruction fetch
#29Preventing multiple translation lookaside buffer accesses for a same page in memory
#30Handling cache miss in an instruction crossing a cache line boundary
#31Prefetching across a page boundary
#32System and method to improve hardware pre-fetching using translation hints
#33Translation lookaside buffer (TLB) suppression for intra-page program counter relative or absolute address branch instructions
#34Fine-grained access memory controller