191562 ⎘
Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures; Details of translation look-aside buffer [TLB] Multi-level TLB, e.g. microTLB and main TLB
ZERO LATENCY PREFETCHING IN CACHES
#2CACHE MANAGEMENT OPERATIONS USING STREAMING ENGINE
#3Controller for locking of selected cache regions
#4Translating virtual memory addresses to physical memory addresses
#5Process dedicated in-memory translation lookaside buffers (TLBs) (mTLBs) for augmenting memory management unit (MMU) TLB for translating virtual addresses (VAs) to physical addresses (PAs) in a processor-based system
#6TRANSLATION LOOKASIDE BUFFER (TLB) PREFETCHER WITH MULTI- LEVEL TLB PREFETCHES AND FEEDBACK ARCHITECTURE
#7HOT PAGE DETECTION BY SAMPLING TLB RESIDENCY
#8Apparatus and method for efficient process-based compartmentalization
#9Zero latency prefetching in caches
#10Translation bandwidth optimized prefetching strategy through multiple translation lookaside buffers
#11Cache Preload Operations Using Streaming Engine
#12Process dedicated in-memory translation lookaside buffers (TLBs) (mTLBs) for augmenting memory management unit (MMU) TLB for translating virtual addresses (VAs) to physical addresses (PAs) in a processor-based system
#13Cache management operations using streaming engine
#14Apparatus and method for efficient process-based compartmentalization
#15Apparatus and method for efficient process-based compartmentalization
#16Process dedicated in-memory translation lookaside buffers (TLBs) (mTLBs) for augmenting memory management unit (MMU) TLB for translating virtual addresses (VAs) to physical addresses (PAs) in a processor-based system
#17Zero latency prefetching in caches
#18Cache structure using a logical directory
#19Using multiple memory elements in an input-output memory management unit for performing virtual address to physical address translations
#20Apparatus and method
#21Cache preload operations using streaming engine
#22Cache management operations using streaming engine
#23Cryptographic computing engine for memory load and store units of a microarchitecture pipeline
#24Multi-engine address translation facility
#25Method and apparatus for an efficient TLB lookup
#26Quality of service for input/output memory management unit
#27Processors, methods, systems, and instructions to load multiple data elements to destination storage locations other than packed data registers
#28Controller for locking of selected cache regions
#29Facilitating access to memory locality domain information
#30Multi-engine address translation facility
#31Multi-engine address translation facility
#32Address translation for scalable linked devices
#33Zero latency prefetching in caches
#34Cache preload operations using streaming engine
#35Cache management operations using streaming engine
#36Intelligently partitioning data cache to allocate space for translation entries
#37Method and apparatus for an efficient TLB lookup
#38Method and apparatus for an efficient TLB lookup
#39MECHANISMS TO ENFORCE SECURITY WITH PARTIAL ACCESS CONTROL HARDWARE OFFLINE
#40Incorporating purge history into least-recently-used states of a translation lookaside buffer
#41Incorporating purge history into least-recently-used states of a translation lookaside buffer
#42Cache structure using a logical directory
#43Cache structure using a logical directory
#44Translation lookaside buffer switch bank
#45Recovery mechanism for low latency metadata log
#46Multi-engine address translation facility
#47Multi-engine address translation facility
#48Streaming translation lookaside buffer
#49Sharing translation lookaside buffer resources for different traffic classes
#50Time-restricted access to file data
#51Apparatus and method for address translation and control of whether an access request is rejected based on an ownership table indicating an owner process for a block of physical addresses
#52Reduced stack usage in a multithreaded processor
#53Programmable memory transfer request processing units
#54Identifying stale entries in address translation cache
#55Apparatus and method for maintaining address translation data within an address translation cache
#56Processors, methods, systems, and instructions to load multiple data elements to destination storage locations other than packed data registers
#57Systems and methods for accessing a unified translation lookaside buffer
#58Reducing over-purging of structures associated with address translation using an array of tags
#59Using multiple memory elements in an input-output memory management unit for performing virtual address to physical address translations
#60Data processing apparatus, and a method of handling address translation within a data processing apparatus
#61Identifying stale entries in address translation cache
#62Supervisory memory management unit
#63Memory management method and device and memory controller
#64Multi-core shared page miss handler
#65Backward compatibility by restriction of hardware resources
#66Systems and methods for accessing a unified translation lookaside buffer
#67Data processing apparatus, controller, cache and method
#68Photonics-Optimized Processor System
#69Multiple stage memory management
#70Memory management for address translation including detecting and handling a translation error condition
#71Address translation in a data processing apparatus
#72Method and apparatus for accessing hardware resource
#73Hiding page translation miss latency in program memory controller by selective page miss translation prefetch
#74Hiding page translation miss latency in program memory controller by next page prefetch on crossing page boundary
#75Method and apparatus for querying physical memory address
#76Method and apparatus for determining physical address
#77Descriptor ring management
#78Multiprocessor computer system
#79Facilitating efficient prefetching for scatter/gather operations
#80Systems and methods for accessing a unified translation lookaside buffer
#81Selective purging of PCI I/O address translation buffer
#82Power efficient level one data cache access with pre-validated tags
#83Device for selecting a level for at least one read voltage
#84Management method of virtual-to-physical address translation system using part of bits of virtual address as index
#85Systems and methods for reducing first level cache energy by eliminating cache address tags
#86System-on-chip and address translation method thereof using a translation lookaside buffer and a prefetch buffer
#87Inter-core cooperative TLB prefetchers
#88Providing metadata in a translation lookaside buffer (TLB)
#89Indexed page address translation to reduce memory footprint in virtualized environments
#90Anticipatorily loading a page of memory
#91Processing device with address translation probing and methods
#92Filtering requests for a translation lookaside buffer
#93Caching of virtual to physical address translations
#94Store operation with conditional push of a tag value to a queue
#95PREFETCHING TABLEWALK ADDRESS TRANSLATIONS
#96Concurrent page table walker control for TLB miss handling
#97STLB prefetching for a multi-dimension engine
#98DMA engine with STLB prefetch capabilities and tethered prefetching
#99System translation look-aside buffer with request-based allocation and prefetching
#100System translation look-aside buffer integrated in an interconnect
#101Using a shared last-level TLB to reduce address-translation latency
#102MEMORY MANAGEMENT IN A VIRTUALIZATION ENVIRONMENT
#103Systems and methods for accessing a unified translation lookaside buffer
#104Multi-core shared page miss handler
#105Providing metadata in a translation lookaside buffer (TLB)
#106MEMORY MANAGEMENT UNIT, APPARATUSES INCLUDING THE SAME, AND METHOD OF OPERATING THE SAME
#107System and method to manage a translation lookaside buffer
#108Data processing apparatus for storing address translations
#109Pre-fetching for a sibling cache
#110Providing metadata in a translation lookaside buffer (TLB)
#111Apparatuses, Systems, and Methods for Reducing Translation Lookaside Buffer (TLB) Lookups
#112Translation look-aside buffer
#113TLB prefetching
#114Processor and address translating method
#115Fast address translation for linear and circular modes
#116SEMICONDUCTOR INTEGRATED CIRCUIT AND ADDRESS TRANSLATION METHOD
#117Method and apparatus for reallocating memory content
#118Arithmetic processing unit and control method for evicting an entry from a TLB to another TLB
#119Calculator and TLB control method
#120System and method for concurrently managing memory access requests
#121Arithmetic processing apparatus, TLB control method, and information processing apparatus
#122Arithmetic processing apparatus and method
#123Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor
#124System, method and computer program product for providing quiesce filtering for shared memory
#125Techniques for multi-level indirect data prefetching
#126Providing metadata in a translation lookaside buffer (TLB)
#127Address translation with multiple translation look aside buffers
#128System and method of improving task switching and page translation performance utilizing a multilevel translation lookaside buffer
#129INSTRUCTION PIPELINE MONITORING DEVICE AND METHOD THEREOF
#130Method to optimize effective page number to real page number translation path from page table entries match resumption of execution stream
#131Miss-under-miss processing and cache flushing
#132Data processor and IP module for data processor
#133Address converting apparatus
#134Updating multiple levels of translation lookaside buffers (TLBs) field
#135Microprocessor with improved data stream prefetching
#136TLB lock indicator
#137Microprocessor including a configurable translation lookaside buffer
#138Scalable DMA remapping on a computer bus
#139Translation look-aside buffer supporting mutually untrusted operating systems
#140System and method of improving task switching and page translation performance utilizing a multilevel translation lookaside buffer
#141Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor
#142Method to optimize effective page number to real page number translation path from page table entries match resumption of execution stream
#143Method and apparatus for address translation
#144Information processing apparatus and software pre-fetch control method
#145Data processor and IP module for data processor
#146System and method for encoding page size information
#147Address translation using a page size tag
#148Apparatus and method for determining a physical address from a virtual address by using a hierarchical mapping regulation with compressed nodes
#149Gathering translation entry invalidation requests in a data processing system
#150Range based flushing mechanism
#151Fine-grained access memory controller