191612 ⎘
Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units; Interrupt Dispatching of interrupt load among interrupt handlers in processor system or interrupt controller
QUEUE BYPASSING INTERRUPT HANDLING
#2Adaptive Interrupt Coalescing
#3CIRCUITRY SYSTEM AND METHOD FOR PROCESSING INTERRUPT PRIORITY
#4Managing efficient selection of a particular processor thread for handling an interrupt
#5Techniques for issuing interrupts in a data processing system with multiple scopes
#6Techniques for issuing interrupts in a data processing system with multiple scopes
#7Techniques for issuing interrupts in a data processing system with multiple scopes
#8Pessimistic interrupt affinity for devices
#9IC card and IC card system having suspend/resume functions
#10Pessimistic interrupt affinity for devices
#11IC card and IC card system having suspend/resume functions
#12Interrupt controller and method of operation of an interrupt controller
#13Event-based debug, trace, and profile in device with data processing engine array