191621 ⎘
Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units; DMA Space or buffer allocation for DMA transfers
METHODS FOR AN AI ACCELERATOR INTEGRATED CIRCUIT CHIP WITH INTEGRATED CELL-BASED FABRIC ADAPTER
#2PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe) DEVICE METHOD FOR DELAYING COMMAND OPERATIONS BASED ON GENERATED THROUGHPUT ANALYSIS INFORMATION
#3INPUT AND OUTPUT SPATIAL CROPPING OPERATIONS IN NEURAL PROCESSOR CIRCUITS
#4ACCELERATION OF NETWORK INTERFACE DEVICE TRANSACTIONS USING COMPUTE EXPRESS LINK
#5SHARED DYNAMIC BUFFER IN IMAGE SIGNAL PROCESSOR
#6PACKET FORWARDING APPARATUS WITH BUFFER RECYCLING AND ASSOCIATED PACKET FORWARDING METHOD
#7Asymmetric read / write architecture for enhanced throughput and reduced latency
#8Peripheral component interconnect express (PCIe) device method for delaying command operations based on generated throughput analysis information
#9SYSTEMS AND METHODS FOR ENABLING CONCURRENT APPLICATIONS TO PERFORM EXTREME WIDEBAND DIGITAL SIGNAL PROCESSING WITH MULTICHANNEL COHERENCY
#10Computing system for transmitting completion early between serially connected electronic devices
#11Fixed ethernet frame descriptor
#12Semiconductor device and systems using the same
#13Apparatus and method for processing burst read transactions
#14Elastic method of remote direct memory access memory advertisement
#15Fixed ethernet frame descriptor
#16Bit manipulation capable direct memory access
#17Direct memory access for co-processor memory
#18Computer and control method for computer
#19Storage apparatus accessed by using memory bus
#20Optimized credit return mechanism for packet sends
#21Engine architecture for processing finite automata
#22Throughput in openfabrics environments
#23Optimized credit return mechanism for packet sends
#24Method and apparatus for protecting a PCI device controller from masquerade attacks by malware
#25Optimized credit return mechanism for packet sends
#26Opportunistic cache injection of data into lower latency levels of the cache hierarchy
#27System and method for supporting a lazy sorting priority queue in a computing environment
#28Direct memory access controller, control method thereof, and information processing system
#29System and method to traverse a non-deterministic finite automata (NFA) graph generated for regular expression patterns with advanced features
#30Memory management for finite automata processing
#31Engine architecture for processing finite automata
#32Generating a non-deterministic finite automata (NFA) graph for regular expression patterns with advanced features
#33System and method for assigning memory access transfers between communication channels
#34Shared and managed memory unified access
#35Multi-lane concurrent bag for facilitating inter-thread communication
#36Asymmetric read / write architecture for enhanced throughput and reduced latency
#37Methods and systems for direct memory access operations