191655 ⎘
Method for data-driven comparison of aerodynamic simulations
#2CONNECTOR WEAR CORRELATION AND PREDICTION ANALYSIS
#3Battery Emulator with Controllable Frequency Response
#4Methods to generate a wiring schema
#5Synthetic scenario simulator based on events
#6Synthetic scenario generator based on attributes
#7Circuit layout similarity metric for semiconductor testsite coverage
#8Automated production optimization technique for smart well completions using real-time nodal analysis including comingled production calibration
#9Preston matrix generator
#10Predictive spatial digital design of experiment for advanced semiconductor process optimization and control
#11Physical simulation test method for detecting position of ponding goaf in excavation
#12Hardware simulation systems and methods for identifying state-holding loops and oscillating loops
#13Shifting a forming limit curve based on zero friction analysis
#14Identifying defect sensitive codes for testing devices with input or output code
#15UNIFIED GEOMETRIES FOR DYNAMIC HIGH-PERFORMANCE COMPUTING
#16Systems and methods for automatically realizing models for co-simulation
#17System and method for interactively controlling the course of a functional simulation
#18Age estimator for safety monitoring based on local detectors
#19Livelock detection in a hardware design using formal evaluation logic
#20VEHICLE DURABILITY MODELING
#21Activity coverage assessment of circuit designs under test stimuli
#22Integrated circuit security
#23Electrical mask validation
#24Synthesis for random testability using unreachable states in integrated circuits
#25OPTIMIZATION OF RESONATOR DESIGN BY ASSESSING IMPACT ON SYSTEM INSTABILITY
#26Care area generation by detection optimized methodology
#27Method for creating prototype and apparatus therefor
#28Standard cell library, integrated circuit including synchronous circuit, and computing system for designing the integrated circuit
#29Circuit structures to resolve random testability
#30Circuit structures to resolve random testability
#31Integrated circuit security
#32System and method for simulating reliability of circuit design
#33Low-power test compression for launch-on-capture transition fault testing
#34PERFORMANCE TESTING METHOD AND APPARATUS FOR INDUSTRIAL SYSTEM DEPLOYED ON CLOUD
#35METHOD FOR DESIGNING AND DIMENSIONING A NEW PART OF A MOTOR VEHICLE
#36Methods for detecting an imminent power failure in time to protect local design state
#37Artificial intelligence engine for mixing and enhancing features from one or more trained pre-existing machine-learning models
#38Process based metrology target design
#39Control of a device with respect to its numerical model
#40Design-for-testability (DFT) insertion at register-transfer-level (RTL)
#41Test capability-based printed circuit board assembly design
#42Techniques for designing interactive objects with integrated smart devices
#43Methods and systems for inverting a simulation process to validate a product design
#44Efficient execution of alternating automaton representing a safety assertion for a circuit
#45System and method for predicting fatigue strength of alloys
#46MODEL VALIDATION SYSTEM AND METHOD
#47Physically aware test patterns in semiconductor fabrication
#48High speed I/O pinless structural testing
#49Comparison and selection of experiment designs
#50Comparison and selection of experiment designs
#51System and method for generation of an integrated circuit design
#52System and method for generation of an integrated circuit design
#53Placing and routing debugging logic
#54Physically aware test patterns in semiconductor fabrication
#55Variation-aware design analysis
#56Method and apparatus for constructing test scenario of unmanned vehicles
#57Global optimization of networks of locally fitted objects
#58Feed-forward for silicon inspections (DFM2CFM : design to silicon) and feed-back for weakpoint predictor decks (CFM2DFM : silicon to design) guided by marker classification, sampling, and higher dimensional analysis
#59Livelock detection in a hardware design using formal evaluation logic
#60Continuously provisioning large-scale machine learning models
#61Inspecting a wafer using image and design information
#62System and method for generation of an integrated circuit design
#63Human-computer combination quality testing system for digital product testing and testing method thereof
#64Method for creating prototype and apparatus therefor
#65Apparatus and method for a scalable test engine
#66Identification of unknown sources for logic built-in self test in verification
#67Information processing by interpenetrating signal transmission channel in design for testability of chip
#68CUSTOMIZED LUMBAR SPINE RESPONSE FINITE ELEMENT MODEL FOR CRASH TEST DUMMY AND METHOD
#69Searchable database of trained artificial intelligence objects that can be reused, reconfigured, and recomposed, into one or more subsequent artificial intelligence models
#70Multiple user interfaces of an artificial intelligence system to accommodate different types of users solving different types of problems with artificial intelligence
#71Graphical user interface to an artificial intelligence engine utilized to generate one or more trained artificial intelligence models
#72Memory access signal detection utilizing a tracer DIMM
#73Power-aware dynamic encoding
#74Level faults interception in integrated circuits
#75Placing and routing debugging logic
#76Method to improve analog fault coverage using test diodes
#77Integrated circuit verification using parameterized configuration
#78Horizontal infrastructure handling for integrated circuit devices
#79Circuit information generating apparatus and circuit information generating system
#80Graphical specification and constraint language for developing programs for hardware implementation and use
#81Exploiting the scan test interface for reverse engineering of a VLSI device
#82Method and apparatus for validating a test pattern
#83Clock-domain-crossing specific design mutations to model silicon behavior and measure verification robustness
#84Method and apparatus for design of a metrology target
#85Method of determining wave propagation in a medium
#86Multiple-capture DFT method for detecting or locating crossing clock-domain faults during self-test or scan-test
#87Semiconductor having cross coupled structure and layout verification method thereof
#88Age estimator for safety monitoring based on local detectors
#89METHOD AND COMPILING SYSTEM FOR GENERATING TESTBENCH FOR IC
#90Replacement method for scan cell of integrated circuit, skewable scan cell and integrated circuit
#91System for and method of semiconductor fault detection
#92Correlation of test results and test coverage for an electronic device design
#93Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test
#94Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test
#95Systems and methods for increasing debugging visibility of prototyping systems
#96Scan cell assignment
#97Logic analyzer circuit for programmable logic device
#98Integrated circuit and method for establishing scan test architecture in integrated circuit
#99System and method for improved transaction based verification of design under test (DUT) to minimize bogus fails
#100Shared channel masks in on-product test compression system
#101Shared channel masks in on-product test compression system
#102Dynamic yield prediction
#103Scan cell selection for partial scan designs
#104Area array device connection structures with complimentary warp characteristics
#105Method for checking a hardware-configurable logic circuit for faults
#106Method of making semiconductor device and system for performing the same
#107Method of making semiconductor device and a control system for performing the same
#108Transmitting LSB timestamp datum in parallel and MSB in series
#109Layout content analysis for source mask optimization acceleration
#110Interposer defect coverage metric and method to maximize the same
#111Graphical specification and constraint language for developing programs for hardware implementation and use
#112Circuit design support method, computer product, and circuit design support apparatus
#113Area array device connection structures with complimentary warp characteristics
#114Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test
#115Systems and methods for dynamic scan scheduling
#116Method and system for designing 3D semiconductor package
#117Correlation of device manufacturing defect data with device electrical test data
#118Systems and methods for integrated circuit C4 ball placement
#119Apparatus for design assist and method for selecting signal line onto which test point for test controlling is to be inserted in circuit to be designed
#120Method of integrated circuit scan clock domain allocation and machine readable media thereof
#121Method and apparatus for optimizing memory-built-in-self test
#122Computer-aided design (CAD) multiple-capture DFT system for detecting or locating crossing clock-domain faults
#123Pattern-dependent proximity matching/tuning including light manipulation by projection optics
#124Method for creating a photolithography mask
#125Generation of memory structural model based on memory layout
#126System and method for lithography simulation
#127Analysis optimizer
#128Process aware metrology
#129Generation method, storage medium, and information processing apparatus
#130Circuit assembly yield prediction with respect to manufacturing process
#131Power balanced pipelines
#132Layout content analysis for source mask optimization acceleration
#133Apparatus and method for designing semiconductor device, and semiconductor device
#134Semiconductor sensor reliability
#135Suspect logical region synthesis from device design and test information
#136Developing programs for hardware implementation in a graphical specification and constraint language
#137Simulation parameter correction technique
#138Method and system for identifying potential causes of failure in simulation runs using machine learning
#139Method and system for generating validation tests
#140Power and scan resource reduction in integrated circuit designs having shift registers
#141Method and system of evaluation of validity of a refinement rule for a hardware emulation
#142Explaining illegal combinations in combinatorial models
#143OPC method with higher degree of freedom
#144Optimized design verification of an electronic circuit
#145Computational thermal analysis during microchip design
#146Managing aging of silicon in an integrated circuit device