191661 ⎘
Method and apparatus for improved circuit structure thermal reliability on printed circuit board materials
#2Clock crossing interface for integrated circuit generation
#3Computer-implemented method, processor-implemented system, and non-transitory computer-readable storage medium storing instructions for simulation of printed circuit board
#4Bump layout for coplanarity improvement
#5Method of selecting routing resources in a multi-chip integrated circuit device
#6Selection of die and package parasitic for IO power domain
#7Chip temperature computation method and chip temperature computation device
#8Via architecture for increased density interface
#9Single simulation-based structure function mapping
#10Interposer for an integrated system and corresponding design method
#11Methods and apparatus providing a graded package for a semiconductor
#12Method of tuning components within an integracted circuit device
#13Thermal resistance analysis model and semiconductor integrated circuit
#14Integrated fan-out package and layout method thereof
#15Redistribution layer routing for integrated fan-out wafer-level chip-scale packages
#16Hybrid modeling for a device under test associated with a two-phase cooling system
#17Package substrate differential impedance optimization for 25 to 60 Gbps and beyond
#18Entry finder for single layer differential group routing
#192.5D electronic package
#20Semiconductor devices with bump allocation
#21ELECTRONIC SYSTEM, AS WELL AS MANUFACTURING METHOD, AND DEVICE FOR MANUFACTURING AN ELECTRONIC SYSTEM
#22Semiconductor devices with ball strength improvement
#23Semiconductor device design methods and conductive bump pattern enhancement methods
#24Method and apparatus for flip chip packaging co-design and co-designed flip chip package
#25Multi-layer circuit using metal layers as a moisture diffusion barrier for electrical performance
#26Computer-implemented method of designing a modularized stacked integrated circuit
#27Circuit design layout in multiple synchronous representations
#28SEMICONDUCTOR DESIGN METHOD AND COMPUTER-READABLE RECORDING MEDIUM
#29Layout method for printed circuit board
#30Area array device connection structures with complimentary warp characteristics
#31Integrated circuit package and method
#32Method for co-designing flip-chip and interposer
#33Method for flip chip packaging co-design
#34Semiconductor device design methods and conductive bump pattern enhancement methods
#35Structure for logic circuit and serializer-deserializer stack
#36Interposer defect coverage metric and method to maximize the same
#37Semiconductor devices with ball strength improvement
#38ASYMMETRIC MESH NOC TOPOLOGIES
#39Apparatus and method for aiding in designing electronic circuits
#40Area array device connection structures with complimentary warp characteristics
#41Integrated circuit floorplan for compact clock distribution
#42System and method for designing semiconductor package using computing system, apparatus for fabricating semiconductor package including the system, and semiconductor package designed by the method
#43Asymmetric mesh NoC topologies
#44Asymmetric mesh NoC topologies
#45Layout method for printed circuit board
#46Systems and methods for creating frequency-dependent netlist
#47Method for input/output design of chip
#48Method for assigning terminal of semiconductor package, apparatus, and semiconductor package
#49Methods of improving bump allocation for semiconductor devices and semiconductor devices with improved bump allocation
#50Apparatus and method for aiding in designing electronic circuits
#51Methods, systems, and computer-readable media for simulating interconnects in electronic packaging structures
#52Modeling of multi-layered power/ground planes using triangle elements
#53Method to optimize and reduce integrated circuit, package design, and verification cycle time
#54Package substrate differential impedance optimization for 25 to 60 GBPS and beyond
#55Light source and method for making a light source
#56Methods, systems, and computer program product for implementing a layout-driven, multi-fabric schematic design
#572.5D electronic package
#58Methods, systems, and articles of manufacture for analyzing a multi-fabric electronic design and displaying analysis results for the multi-fabric electronic design spanning and displaying simulation results across multiple design fabrics
#59Method, system, and computer program product for checking, verifying, or testing a multi-fabric electronic design spanning across multiple design fabrics
#60Method, system, and computer program product for implementing a multi-fabric electronic design spanning across multiple design fabrics
#61Asymmetric mesh NoC topologies