Clock crossing interface for integrated circuit generation

Clock gate latency modeling based on analytical frameworks

Hierarchical clock tree construction based on constraints

Optimally driving non-uniform clock mesh loads

Clock tree synthesis method

System and method for a hybrid current-mode and voltage-mode integrated circuit

Phase algebra for virtual clock and mode extraction in hierarchical designs

Verifying sequential equivalence for randomly initialized designs

Distributed programmable delay lines in a clock tree

Constructing staging trees in hierarchical circuit designs

Techniques based on electromigration characteristics of cell interconnect

Cell layout of semiconductor device

INTEGRATED CIRCUIT, SCAN SHIFT CONTROL METHOD, AND CIRCUIT DESIGN METHOD

Automatic multi-clock circuit generation

Formal clock network analysis, visualization, verification and generation

Reducing clock power consumption of a computer processor

Reducing clock power consumption of a computer processor

Parameter collapsing and corner reduction in an integrated circuit

Parameter collapsing and corner reduction in an integrated circuit

Parameter collapsing and corner reduction in an integrated circuit

Multi-die IC layout methods with awareness of mix and match die integration

Verification support apparatus and design verification support method

Clock network analysis using harmonic balance

Structure and generation method of clock distribution network

DYNAMIC CONFIGURATION OF A RECONFIGURABLE HUM FABRIC

Simulation system with clock and messaging synchronization

Block-level design method for heterogeneous PG-structure cells

Generating a layout for an integrated circuit

ACCOMMODATING ENGINEERING CHANGE ORDERS IN INTEGRATED CIRCUIT DESIGN

ACCOMMODATING ENGINEERING CHANGE ORDERS IN INTEGRATED CIRCUIT DESIGN

Callback based constraint processing for clock domain independence

Clock jitter emulation

Phase algebra for analysis of hierarchical designs

Formal method for clock tree analysis and optimization

Circuit design analyzer

Glitch-aware phase algebra for clock analysis

Programmable clock division methodology with in-context frequency checking

Callback based constraint processing for clock domain independence

Reset domain crossing management using unified power format

Clock tree synthesis based on computing critical clock latency probabilities

Methods and Computer-Readable Media for Synthesizing a Multi-Corner Mesh-Based Clock Distribution Network for Multi-Voltage Domain and Clock Meshes and Integrated Circuits

Method and system for functional verification and power analysis of clock-gated integrated circuits

Using deep sub-micron stress effects and proximity effects to create a high performance standard cell

Clock domain-independent abstracts

Accommodating engineering change orders in integrated circuit design

Accommodating engineering change orders in integrated circuit design

Integrated circuit with multi-bit clock gating cells

Graphical analysis of complex clock trees

METHODS AND SYSTEMS FOR FUNCTIONAL ANALYSIS OF AN INTEGRATED CIRCUIT

Flip-flop clustering for integrated circuit design

Clock circuit and clock signal transmission method thereof

Techniques based on electromigration characteristics of cell interconnect

Controlling real time during embedded system development

Generating a layout for an integrated circuit

Generating a layout for an integrated circuit

Clock jitter emulation

Overlaying of clock and data propagation in emulation

System and process for simulating the behavioral effects of timing violations between unrelated clocks

Cell layout of semiconductor device

Power-density-based clock cell spacing

Accurate glitch detection

Validating a clock tree delay

Method and apparatus for automatic relative placement generation for clock trees

Iterative solution using compressed inductive matrix for efficient simulation of very-large scale circuits

Power savings method in a clock mesh-based design through a smart decloning technique

Clock placement for programmable logic devices

Level balanced clock tree

Data propagation analysis for debugging a circuit design

Generating clock on demand

System and method for netlist clock domain crossing verification

Configurable cell design using capacitive coupling for enhanced timing closure

Distributed LC resonant tanks clock tree synthesis

Multi-mode multi-corner clocktree synthesis

Phase algebra for virtual clock and mode extraction in hierarchical designs

Phase algebra for specifying clocks and modes in hierarchical designs

Timing violation resilient asynchronous template

Multiple-capture DFT method for detecting or locating crossing clock-domain faults during self-test or scan-test

Systems and methods for flexibly optimizing processing circuit efficiency

Conditional phase algebra for clock analysis

Clock-tree transformation in high-speed ASIC implementation

Clock tree synthesis graphical user interface

Clock-gating phase algebra for clock analysis

Circuit design analyzer

LSI DESIGN METHOD

Clock skew adjusting structure

Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test

Timing violation resilient asynchronous template

Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test

Methods and computer-readable media for synthesizing a multi-corner mesh-based clock distribution network for multi-voltage domain and clock meshes and integrated circuits

Method and design apparatus

Phase algebra for analysis of hierarchical designs

Network flow based framework for clock tree optimization

Methods for static checking of asynchronous clock domain crossings

Integrated circuit clock tree visualizer

Method and apparatus for automatic relative placement generation for clock trees

System for and method of placing clock stations using variable drive-strength clock drivers built out of a smaller subset of base cells for hybrid tree-mesh clock distribution networks

System for and method of combining CMOS inverters of multiple drive strengths to create tune-able clock inverters of variable drive strengths in hybrid tree-mesh clock distribution networks

Phase algebra for analysis of hierarchical designs

Verification of asynchronous clock domain crossings

Circuit design evaluation with compact multi-waveform representations

Static checking of asynchronous clock domain crossings

Conditional phase algebra for clock analysis

Clock-gating phase algebra for clock analysis

Glitch-aware phase algebra for clock analysis

Method of Designing Semiconductor Device, Designing Assistance Program, Designing Apparatus, and Semiconductor Device

Monolithic three dimensional (3D) integrated circuit (IC) (3DIC) cross-tier clock skew management systems, methods and related components

Register clustering for clock network topology generation

CIRCUIT DESIGN SUPPORT METHOD, COMPUTER PRODUCT, CIRCUIT DESIGN SUPPORT APPARATUS, AND SEMICONDUCTOR INTEGRATED CIRCUIT

Transmitting LSB timestamp datum in parallel and MSB in series

Dynamically selecting master clock to manage non-linear simulation clocks

Dynamic control of design clock generation in emulation

Determining a set of timing paths for creating a circuit abstraction

Hierarchical verification of clock domain crossings

Specifying and implementing relative hardware clocking in a high level programming language

Clock tree construction across clock domains

Dual-structure clock tree synthesis (CTS)

Wafer masks, semiconductor device, and computer aided fabrication system for distributed LC resonant tanks and clock tree synthesis

Generating clock on demand

Automatic synthesis of complex clock systems

Setting switch size and transition pattern in a resonant clock distribution system

Multiple-capture DFT system for detecting or locating crossing clock-domain faults during scan-test

Semiconductor device design method and design apparatus

Data transfer across power domains

Clock distribution network for 3D integrated circuit

Packet switch based logic replication

Voltage-aware signal path synchronization

Computer-aided design (CAD) multiple-capture DFT system for detecting or locating crossing clock-domain faults

LSI design method

Macro timing analysis device, macro boundary path timing analysis method and macro boundary path timing analysis program

Clock-tree transformation in high-speed ASIC implementation

System and method for clock network meta-synthesis

Method and apparatus for automatic relative placement generation for clock trees

Multi-mode multi-corner clocktree synthesis

Verification of asynchronous clocking systems

Dynamically selecting master clock to manage non-linear simulation clocks

Controlling real time during embedded system development

Multi-bit clock gating cell to reduce clock power

Targeted delay optimization through programmable clock delays

Clock control trees

Timing-closure methodology involving clock network in hardware designs

Bisection methodology for on-chip variation tolerant clock signal distribution in an integrated circuit

Systems and methods for clock tree clustering

Multi-mode multi-corner clocktree synthesis

Efficient system debug infrastructure for tiled architecture

Generating clock trees for a circuit design

Systems and methods for power efficient flop clustering

Placement and routing of clock signals for a circuit design

Methods, systems, and articles of manufacture for verifying an electronic design using hierarchical clock domain crossing verification techniques

Dynamic tag allocation for clock reconvergence pessimism removal

Integrated circuit retiming with selective modeling of flip-flop secondary signals

Method and system for functional verification and power analysis of clock-gated integrated circuits

Method for gating clock signals using late arriving enable signals

Register retiming and verification of an integrated circuit design

Clock region partitioning and clock routing

Methods, systems, and apparatus for clock topology planning with reduced power consumption

Machine readable products for single pass parallel hierarchical timing closure of integrated circuit designs