Creating and reusing customizable structured interconnects

Force/release support in emulation and formal verification

Tapped inductor voltage controlled oscillator

Photoresist design layout pattern proximity correction through fast edge placement error prediction via a physics-based etch profile modeling framework

Integrated circuit security

Integrated circuit security

Effective substitution of global distributed head switch cells with cluster head switch cells

Tapped inductor voltage controlled oscillator

Creating and reusing customizable structured interconnects

Application specific integrated circuit (ASIC) test screens and selection of such screens

Tapped inductor voltage controlled oscillator

Communicating configuration information across a programmable analog tile to another tile

Partial update in a ternary content addressable memory

Partial update in a ternary content addressable memory

Diagnosis device, control method of diagnosis device, and recording medium

Structure for logic circuit and serializer-deserializer stack

METHOD FOR PRODUCING A DPA-RESISTANT LOGIC CIRCUIT

VLSI layouts of fully connected generalized and pyramid networks with locality exploitation

Method and system for reproducing prototyping failures in emulation

Microelectromechanical system design and layout

Automated metal pattern generation for integrated circuits

Method of designing a high performance application specific integrated circuit accelerator

Forwarding element integrated circuit chip with separate I/O and switching tiles

Method and apparatus for improving a design for a system during compilation by performing network replacement

Method and apparatus for performing register retiming by utilizing native timing-driven constraints

Systems and methods for finite difference time domain simulation of an electronic design

Selecting predefined circuit implementations in a circuit design system

Partitioning a system graph for circuit simulation to obtain an exact solution