191668 ⎘
System and method for implementing verification IP for pre-silicon functional verification of a layered protocol
#2System and method for application specific integrated circuit design
#3Layout of large block synthesis blocks in integrated circuits
#4Network-on-chip for inter-die and intra-die communication in modularized integrated circuit devices
#5Adaptive multi-tier power distribution grids for integrated circuits
#6Die to die interconnect structure for modularized integrated circuit devices
#7Integrated circuit security
#8System and method for application specific integrated circuit design
#9Layout of large block synthesis blocks in integrated circuits
#10Layout of large block synthesis blocks in integrated circuits
#11Integrated circuit security
#12Effective substitution of global distributed head switch cells with cluster head switch cells
#13Methods and systems for system design automation (SDA) of mixed signal electronic circuitry including embedded software designs
#14Adaptive multi-tier power distribution grids for integrated circuits
#15Optimizing an integrated circuit (IC) design comprising at least one wide-gate or wide-bus
#16Layout of large block synthesis blocks in integrated circuits
#17Layout of large block synthesis blocks in integrated circuits
#18Integrated circuit design using generation and instantiation of circuit stencils
#19Reuse of extracted layout-dependent effects for circuit design using circuit stencils
#20Semiconductor LSI design device and design method
#21Formal verification driven power modeling and design verification
#22Power consumption estimation method for system on chip (SOC), system for implementing the method
#23Apparatus and method for a scalable test engine
#24Reuse of extracted layout-dependent effects for circuit design using circuit stencils
#25Rectilinear macros having non-uniform channel spacing
#26Configuring a programmable device using high-level language
#27Method and apparatus for modeling multi-terminal MOS device for LVS and PDK
#28Method and apparatus of a three dimensional integrated circuit
#29Method for decomposing a hardware model and for accelerating formal verification of the hardware model
#30System, method and computer-accessible medium for facilitating logic encryption
#31System-on-chip intellectual property block discovery
#32System on chip
#33Multi-project wafer with IP protection by reticle mask pattern modification
#34Third party component debugging for integrated circuit design
#35Configuring a programmable device using high-level language
#36LSI designing apparatus, LSI designing method, and program
#37Identifying hierarchical chip design intellectual property through digests
#383D floorplanning using 2D and 3D blocks
#39Asymmetric mesh NoC topologies
#40Asymmetric mesh NoC topologies
#41Mixed signal IP core prototyping system
#42Verification module apparatus for debugging software and timing of an embedded processor design that exceeds the capacity of a single FPGA
#43Microelectromechanical system design and layout
#44Third party component debugging for integrated circuit design
#45IP protection
#46Computer product, IP model generating apparatus, and IP model generating method
#47System and method for three-dimensional schematic capture and result visualization of multi-physics system models
#48Integrated circuit simulation with data persistency for efficient memory usage
#49Formal verification driven power modeling and design verification
#50Formal verification driven power modeling and design verification
#51Selecting predefined circuit implementations in a circuit design system
#52Asymmetric mesh NoC topologies
#53Management system, method and apparatus for licensed delivery and accounting of electronic circuits