191669 ⎘
Clock crossing interface for integrated circuit generation
#2Vias with multiconnection via structures
#3Peripheral tool
#4Apparatus and method of operating timing analysis considering multi-input switching
#5Preston matrix generator
#6Hardware incremental model checking verification
#7Microprocessor including an efficiency logic unit
#8Method and system for hierarchical circuit simulation using parallel processing
#9Modeling superconducting quantum circuit systems
#10Method for routing bond wires in system in a package (SiP) devices
#11Modifying a manufacturing process of integrated circuits based on large scale quality performance prediction and optimization
#12Electrical mask validation
#13Method and system for converting a single-threaded software program into an application-specific supercomputer
#14Modeling a bus for a system design incorporating one or more programmable processors
#15STOCHASTIC DATAFLOW ANALYSIS FOR PROCESSING SYSTEMS
#16Modifying a manufacturing process of integrated circuits based on large scale quality performance prediction and optimization
#17Device for simulating multicore processors
#18Reducing clock power consumption of a computer processor
#19Reducing clock power consumption of a computer processor
#20Dynamic microprocessor gate design tool for area/timing margin control
#21Method for simulating execution of an application on a multi-core processor
#22DEVELOPMENT, PROGRAMMING, AND DEBUGGING ENVIRONMENT
#23Modeling superconducting quantum circuit systems
#24Error checking of a multi-threaded computer processor design under test
#25SYSTEM AND METHOD FOR SEISMIC INVERSION
#26Method, apparatus and system for automatically deriving parameters for an interconnect
#27Dynamic microprocessor gate design tool for area/timing margin control
#28Target capture and replay in emulation
#29Modeling a bus for a system design incorporating one or more programmable processors
#30Information processing device that executes simulation and a simulation method
#31Multi-language / multi-processor infusion pump assembly
#32In-cycle resource sharing for high-level synthesis of microprocessors
#33Method and system for converting a single-threaded software program into an application-specific supercomputer
#34Look-ahead timing prediction for multi-instance module (MIM) engineering change order (ECO)
#35Generating design structure for microprocessor with arithmetic logic units and an efficiency logic unit
#36Structure for microprocessor including arithmetic logic units and an efficiency logic unit
#37Voltage scaling for holistic energy management
#38Processor stressmarks generation
#39Processor stressmarks generation
#40System and method for designing and validating computing systems
#41Method and system for converting a single-threaded software program into an application-specific supercomputer
#42Processor core arrangement, computing system and methods for designing and operating a processor core arrangement
#43Identifying layout pattern candidates
#44Method of generating voltage island for 3D many-core chip multiprocessor
#45Method of Designing Semiconductor Device, Designing Assistance Program, Designing Apparatus, and Semiconductor Device
#46Instruction scheduling approach to improve processor performance
#47Development, programming, and debugging environment
#48Multi-language / multi-processor infusion pump assembly
#49Enabling reuse of unit-specific simulation irritation in multiple environments
#50Method for verification of reconfigurable processor
#51Verifying processor-sparing functionality in a simulation environment
#52Verification module apparatus for debugging software and timing of an embedded processor design that exceeds the capacity of a single FPGA
#53Method to simulate a digital system
#54Method and system for converting a single-threaded software program into an application-specific supercomputer
#55Verifying processor-sparing functionality in a simulation environment
#56Method and apparatus for designing and generating a stream processor
#57System, method and apparatus for a scalable parallel processor
#58Instruction scheduling approach to improve processor performance
#59Method and system for automatic generation of processor datapaths
#60Designing digital processors using a flexibility metric
#61Storage unsharing
#62Instruction scheduling approach to improve processor performance
#63Simulator of multi-core system employing reconfigurable processor cores and method of simulating multi-core system employing reconfigurable processor cores
#64Method and system for trace compaction during emulation of a circuit design
#65Hardware emulation method and system using a port time shift register
#66Compacting trace data generated by emulation processors during emulation of a circuit design