Method and system for latch-up prevention

SYSTEM AND METHOD FOR SELF-HEALING OF A DYNAMIC LINK

3D model validation and optimization system and method thereof

3D MODEL VALIDATION AND OPTIMIZATION SYSTEM AND METHOD THEREOF

Placement-driven generation of error detecting structures in integrated circuits

System and method for isolating faults in a resilient system

3D tolerance analysis system and methods

Automated analog fault injection

Placement-driven generation of error detecting structures in integrated circuits

Three-dimensional NoC reliability evaluation

Skeleton I/O generation for early ESD analysis

Low power VLSI designs using circuit failure in sequential cells as low voltage check for limit of operation

Dynamic link serialization in network-on-chip

COMPUTER-READABLE STORAGE MEDIUM HAVING ELECTRO-STATIC DISCHARGE VERIFICATION PROGRAM STORED THEREIN, INFORMATION PROCESSING APPARATUS, AND METHOD OF VERIFYING ELECTRO-STATIC DISCHARGE

System and method for configuring a plurality of registers with soft error detection and low wiring complexity

Soft-error-rate calculating device

Connectivity-aware layout data reduction for design verification

Integrated circuit device, safety circuit, safety-critical system and method of manufacturing an integrated circuit device

Single event upset mitigation for electronic design synthesis

Sequential state elements radiation hardened by design

Fault tree system reliability analysis system, fault tree system reliability analysis method, and program therefor

In-place resynthesis and remapping techniques for soft error mitigation in FPGA

Reducing performance degradation in backup semiconductor chips

Simulation apparatus and simulation method for determining soft error rates for a configured model

Providing test coverage of integrated ECC logic en embedded memory

Visualization of tradeoffs between circuit designs

Configurable register circuitry for error detection and recovery