191678 ⎘
SIMULATION SYSTEM AND METHOD
#2Over-the-air hardware update
#3Verification complexity reduction via range-preserving input-to-constant conversion
#43D MODEL VALIDATION AND OPTIMIZATION SYSTEM AND METHOD THEREOF
#5Methodology to create constraints and leverage formal coverage analyzer to achieve faster code coverage closure for an electronic structure
#6Co-simulation system with delay compensation and method for control of co-simulation system
#7PROGRAMMATIC BEHAVIORS OF A CONTEXTUAL DIGITAL TWIN
#8Methods and apparatus for profile-guided optimization of integrated circuits
#9Learning framework for software-hardware model generation and verification
#10Method for configuring a co-simulation for a total system
#11GENERATING CIRCUITS
#12Address generators for verifying integrated circuit hardware designs for cache memory
#13Method for creating a model compatible with a simulation device
#14METHOD FOR COMPUTER-SUPPORTED DEVELOPMENT OF AN OVERALL SYSTEM CONSISTING OF SUBSYSTEMS
#15Target capture and replay in emulation
#16Software tool for simulating operation of hardware and software systems
#17ECU for transmitting large data in HiL test environment, system including the same and method thereof
#18System and method for universal control of electronic devices
#19Dynamically loaded system-level simulation
#20Micro-benchmark analysis optimization for microprocessor designs
#21Graphical design verification environment generator
#22True hardware in the loop SPI emulation
#23Closed loop simulation of a computer model of a physical system and an actual real-time hardware component of the physical system
#24Extracting system architecture in high level synthesis
#25System architecture generation
#26Modifying a virtual processor model for hardware/software simulation
#27Method and system for testing control software of a controlled system
#28Graphical design verification environment generator
#29Brake HILS system for a railway vehicle
#30Graphical design verification environment generator
#31Graphical design verification environment generator
#32Dynamically loaded system-level simulation
#33Method and apparatus for electronic system model generation
#34Partial update in a ternary content addressable memory
#35Partial update in a ternary content addressable memory
#36Coherent state among multiple simulation models in an EDA simulation environment
#37Support device, semiconductor device, and non-transitory computer readable medium
#38System and method for universal control of electronic devices
#39Method and system for reproducing prototyping failures in emulation
#40Compilation of system designs
#41Techniques to simulate production events
#42Hardware device for accelerating the execution of a systemC simulation in a dynamic manner during the simulation
#43Simulator generation method and apparatus
#44Simulation method, system, and program
#45Simulating vector execution
#46Method and configuration environment for supporting the configuration of an interface between simulation hardware and an external device
#47Modifying a virtual processor model for hardware/software simulation
#48Simulation execution method, program, and system
#49Embedded system development
#50Specification method for producing data processing systems
#51Simulation apparatus, computer-readable recording medium, and method
#52Coherent state among multiple simulation models in an EDA simulation environment
#53Method and apparatus for electronic system model generation
#54Common shared memory in a verification system
#55Simulating machine and method for determining sensitivity of a system output to changes in underlying system parameters
#56Automated semiconductor design flaw detection system
#57System and method for three-dimensional schematic capture and result visualization of multi-physics system models
#58Method and system for identifying potential causes of failure in simulation runs using machine learning
#59Productivity platform using system-on-chip with programmable circuitry
#60Updating block random access memory contents using memory emulation
#61Partial reconfiguration debugging using hybrid models
#62Method and system for trace compaction during emulation of a circuit design
#63Systems and methods for finite difference time domain simulation of an electronic design
#64Multiprocessing subsystem with FIFO/buffer modes for flexible input/output processing in an emulation system
#65Method and system for modeling a flip-flop of a user design
#66Hardware emulation method and system using a port time shift register
#67Compacting trace data generated by emulation processors during emulation of a circuit design
#68Method and apparatus for performing compilation using multiple design flows
#69Systems and methods for handling interrupts during software design simulation
#70Debuggable opaque IP
#71Simulation that transfers port values of a design block via a configuration block of a programmable device