ALIGNMENT IN HARDWARE ACCELERATORS

DATA ENCODING WITHOUT OVERHEAD

MULTIPLEXOR FOR A PROCESSING UNIT OF MEMORY

SYSTEMS AND METHODS FOR DATA SYNCHRONIZATION

Host Accesses to Processing-in-Memory Oriented Data Structures

COMPILER-BASED SYNCHRONIZATION FOR DATAFLOW GRAPHS ON COARSE-GRAINED RECONFIGURABLE ARCHITECTURES

WAVEFORM GENERATOR

Vector computation unit in a neural network processor

Asynchronous finite state machine output masking with customizable topology

NUCLEIC ACID-BASED DATA STORAGE

NUCLEIC ACID-BASED DATA STORAGE

NUCLEIC ACID-BASED DATA STORAGE

Vector computation unit in a neural network processor

COMPILER-BASED INPUT SYNCHRONIZATION FOR PROCESSOR WITH VARIANT STAGE LATENCIES

Methods and apparatus for synchronizing data transfers across clock domains using heads-up indications

Waveform generator

Nucleic acid-based data storage

Data bus with multi-input pipeline

NUCLEIC ACID-BASED DATA STORAGE

System and a method for controlling timing of processing network data

Matrix normal/transpose read and a reconfigurable data processor including same

Hardware double buffering using a special purpose computational unit

Shifting architecture for data reuse in a neural network

Vector computation unit in a neural network processor

Set buffer state instruction

Storage device including multi data rate memory device and memory controller

Hardware double buffering using a special purpose computational unit

Methods for using nucleic acids to store, retrieve and access information comprising a text, image, video or audio format

Neural network computing

Statically-schedulable feed and drain structure for systolic array architecture

Nucleic acid-based data storage

Link management method and physical device

Methods for retrievable information storage using nucleic acids

Electronic apparatus having parallel memory banks

Self-stuffing multi-clock FIFO requiring no synchronizers

Set buffer state instruction

Lower energy consumption and high speed computer system and a marching main memory adapted for the computer system, without the memory bottleneck

Gate driver circuit

Variable-sized buffers mapped to hardware registers

Shiftable memory employing ring registers

Optimization of native buffer accesses in Java applications on hybrid systems

Optimization of native buffer accesses in Java applications on hybrid systems

Intelligent parametric scratchap memory architecture

MEMORY CONTROLLER AND OPERATION METHOD THEREOF

Circuits and methods for signal transfer between different clock domains

Double data rate output circuit

Method for controlling operation of a memory using a single write location and an associated memory

Data rearranging circuit, variable delay circuit, fast fourier transform circuit, and data rearranging method

Interpreting I/O operation requests from pageable guests without host intervention

Processor embedded memory structure with lower energy consumption and high speed without memory bottleneck

Fast cyclic decoder circuit for FIFO/LIFO data buffer

Double data rate output circuit and method

Interpreting I/O operation requests from pageable guests without host intervention

Systems, pipeline stages, and computer readable media for advanced asynchronous pipeline circuits

APPARATUS AND METHOD FOR TRANSFERRING DATA WITHIN A DATA PROCESSING SYSTEM

Cascadable high-performance instant-fall-through synchronous first-in-first-out (FIFO) buffer

Double data rate output latch for static RAM device has edge-triggered flip-flop to output DDR signal to synchronize with a second clock signal

Digital programmable phase generator

System and method for contextual commands in a search results page

Buffer circuit

Asynchronous ripple pipeline

FIFO REGISTER UNIT AND METHOD THEREOF

Electronic circuit with a fifo pipeline

Digital programmable phase generator

System and method of transmitting data in an electronic circuit

Synchronization circuit and method with transparent latches

System and method for a high-speed shift-type buffer

Interpreting I/O operation requests from pageable guests without host intervention

Synchronous pipeline with normally transparent pipeline stages

FIFO-register and digital signal processor comprising a FIFO-register

Communication clocking conversion techniques

Superconducting digital first-in first-out buffer using physical back pressure mechanism

Scalable-entry FIFO memory device