Unsuccessful write retry buffer

Method for generating information based on FIFO memory and apparatus, device and medium

Unsuccessful write retry buffer

Scalable input/output system and techniques to transmit data between domains without a central processor

Data flow control for multi-chip select

Unsuccessful write retry buffer

Scalable input/output system and techniques to transmit data between domains without a central processor

Control system, control method and nonvolatile computer readable medium for operating the same

Data flow control method and apparatus

Data flow control for multi-chip select

Binary-to-gray conversion circuit, related FIFO memory, integrated circuit and method

Asynchronous buffer with pointer offsets

Real-time hierarchical protocol decoding

Base state for thin-provisioned volumes

Independent tuning of multiple hardware prefetchers

Enhanced performance-aware instruction scheduling

Scalable input/output system and techniques to transmit data between domains without a central processor

System and method for managing data in a ring buffer

Buffer controller, memory device, and integrated circuit device

Managing backend resources via frontend steering or stalls

Method and apparatus for controlling an average fill level of an asynchronous first-in-first-out, FIFO

Collision detection for slave storage devices

Statically-schedulable feed and drain structure for systolic array architecture

Transaction handling

Transitioning a buffer to be accessed exclusively by a driver layer for writing immediate data stream

FIRST-IN FIRST-OUT CONTROL CIRCUIT, STORAGE DEVICE, AND METHOD OF CONTROLLING FIRST-IN FIRST-OUT CONTROL CIRCUIT

Electronic devices and operation methods of the same

DATA THROTTLING FOR HIGH SPEED COMPUTING DEVICES

Communicating signals between divided and undivided clock domains

Pre-allocating memory buffers by physical processor and using a bitmap metadata in a control program

Pre-allocating memory buffers by physical processor and using a bitmap metadata in a control program

FIRST-IN-FIRST-OUT BUFFER

Synchronizing multi-threaded servicing of a server event buffer

FPGA-based interface signal remapping method

Method of and apparatus for controlling overrun when writing data from a display controller to memory

Ring buffer including a preload buffer

Data item order restoration

First-in-first-out buffer

USB enabled base station for a headset

Engine architecture for processing finite automata

Information processing system, information processing method, and information processing device

Packet descriptor storage in packet memory with cache

DISPLAY CONTROLLER

Data flow control for multi-chip-select

Collision detection for slave storage devices

Scalable input/output system and techniques to transmit data between domains without a central processor

Storage Device With Power Management Throttling

Sending packets using optimized PIO write sequences without SFENCES

Adaptive alphanumeric sorting apparatus

Real-time data management for a power grid

Systems and methods for low interference logging and diagnostics

In-memory buffer service

Buffer, semiconductor apparatus and semiconductor system using the same

Sending packets using optimized PIO write sequences without sfences

FIFO memory having a memory region modifiable during operation

METHOD FOR EXCHANGING CONTROLS THROUGH A USB DISC AND RELATIVE DEVICES WHICH ALLOW THE IMPLEMENTATION THEREOF

Adaptive Map-Reduce pipeline with dynamic thread allocations

Approach for chip-level flop insertion and verification based on logic interface definition

Adaptive map-reduce pipeline with dynamic thread allocations

Buffer management method and apparatus for universal serial bus communication in wireless environment

DUAL-CLOCK FIFO APPARATUS FOR PACKET TRANSMISSION

Media playback power management devices and methods

Asynchronous FIFO buffer with Johnson code write pointer

Automatically preventing large block writes from starving small block writes in a storage device

Real-time hierarchical protocol decoding

Data transmitter apparatus and method for data communication using the same

INTEGRATED CIRCUIT AND LOW POWER METHOD OF OPERATION

Control device and control method

In-memory buffer service

Resetting memory locks in a transactional memory system

Resetting memory locks in a transactional memory system

Method and system for queuing data for multiple readers and writers

Dynamic Multi-processing In Multi-core Processors

Real-time data management for a power grid

Fabricating electronic device including a semiconductor memory that comprises an inter-layer dielectric layer with first and second nitride layer over stacked structure

Data transfer apparatus and data transfer method

Method and apparatus for handling incoming data frames

Translation layer for controlling bus access

System and method for efficient buffer management for banked shared memory designs

System and method for despreader memory management

Automatically preventing large block writes from starving small block writes in a storage device

Source-to-source compiler and run-time library to transparently accelerate stack or queue-based irregular applications on many-core architectures

Quantum interference unit, quantum interference device, atomic oscillator, electronic apparatus, and moving object

Interfacing with a buffer manager via queues

Deterministic FIFO buffer

Virtual load store queue having a dynamic dispatch window with a distributed structure

Virtual load store queue having a dynamic dispatch window with a unified structure

System and method to traverse a non-deterministic finite automata (NFA) graph generated for regular expression patterns with advanced features

Memory management for finite automata processing

Engine architecture for processing finite automata

Generating a non-deterministic finite automata (NFA) graph for regular expression patterns with advanced features

Techniques for increasing instruction issue rate and reducing latency in an out-of order processor

Software interface for a specialized hardware device

SEMICONDUCTOR MEMORY DEVICE HAVING DATA COMPRESSION TEST CIRCUIT

Buffer memory reservation techniques for use with a NAND flash memory

Low latency first-in-first-out (FIFO) buffer

System and method for efficient buffer management for banked shared memory designs

Apparatus including buffer allocation management and related methods

Virtual channel for data transfers between devices

Data processing apparatus and data processing method

Software interface for a specialized hardward device

Multiple, per sensor configurable FIFOs in a single static random access memory (SRAM) structure

Arithmetic processing apparatus and control method of arithmetic processing apparatus

Intelligent data buffering between interfaces

Dual-buffer serialization and consumption of variable-length data records produced by multiple parallel threads

Electronic system subject to memory overflow condition

Method of operating data compression circuit and devices to perform the same

Storage device and method for reallocating storage device resources based on an estimated fill level of a host buffer

Incident handling

Folded FIFO memory generator

Reducing delay and delay variation in a buffer in network communications

Real-time data management for a power grid

Data transfer device and method

GPU memory buffer pre-fetch and pre-back signaling to avoid page-fault

Method and apparatus for recovering memory of user plane buffer

Automatically preventing large block writes from starving small block writes in a storage device

Elastic buffer module and elastic buffering method for transmission interface

Alignment for multiple FIFO pointers

Writing message to controller memory space

First-in first-out memory device and electronic apparatus having the same

Communication processing device that stores communication data in buffers, image forming apparatus, and method of communication processing

System for managing buffers of time-stamped events

Controller for storage device and method for controlling storage device

DATA READING DEVICE, COMMUNICATION DEVICE, DATA READING METHOD AND PROGRAM

Method and apparatus for buffer initialization

Efficient low-latency buffer

Data storage for voltage domain crossings

Apparatus including buffer allocation management and related methods

Semiconductor memory device having data compression test circuit

Virtual notes in a reality overlay

Concurrently applying an image file while it is being downloaded using a multicast protocol

Low latency first-in-first-out (FIFO) buffer

Media playback power management devices and methods

Efficient low-latency buffer

Inter-clock domain data transfer FIFO circuit

Sequential-write, random-read memory

Efficient low-latency buffer

Digital phase relationship lock loop

BUFFER CONTROL DEVICE AND BUFFER MEMORY DEVICE

Ring buffer circuit and control circuit for ring buffer circuit

Efficient buffer utilization in a computer network-based messaging system

Virtual notes in a reality overlay

METHOD, APPARATUS AND COMPUTER PROGRAM PRODUCT FOR PROVIDING IMPROVED MEMORY USAGE

Digital phase relationship lock loop

Compute unit with an internal bit FIFO circuit

Hybrid buffer management

Reset system for buffer and method thereof

Clock synchronization of data streams

Method for reading out sensor data

METHOD, SYSTEM AND RELATED SYNCHRONIZER FOR CONTROLLING DATA SYNCHRONIZATION IN FIFO MEMORIES

Buffer controller, codec and methods for use therewith

Control device for controlling a buffer memory

Managing queues

Data management in long record length memory

Buffering data during data transfer through a plurality of channels

Asynchronous first-in-first-out cell

Lock-free bounded FIFO queue mechanism

Adaptive play-out buffers and adaptive clock operation in packet networks

Synchronizer for multi-rate input data using unified first-in-first-out memory and method thereof

Digital phase relationship lock loop

Buffer management system, digital audio receiver, headphones, loudspeaker, method of buffer management

Message management methods and apparatus for audio storage systems

Method and apparatus for queue depth detection in a memory system

Method and apparatus for transferring data

System and method for implementing a demand paging jitter buffer algorithm

Decimation of fixed length queues having a number of position for holding data wherein new data is favored over old data

Elastic buffer

Synchronization of active flag and status bus flags in a multi-queue first-in first-out memory system

Multiple counters to relieve flag restriction in a multi-queue first-in first-out memory system

Mark/re-read and mark/re-write operations in a multi-queue first-in first-out memory system

Flow through asynchronous elastic FIFO apparatus and method for implementing multi-engine parsing and authentication

Method of managing a device for memorizing data organized in a queue, and associated device

Buffer management via non-data symbol processing for a point to point link

Method and apparatus for controlling amount of buffer data in a receiver of a data communication system, and method and apparatus for playing streaming data with adaptive clock synchronization unit

First-in first-out memory system with shift register fill indication

First-in first-out memory system with single bit collision detection

FIFO memory with single port memory modules for allowing simultaneous read and write operations

Apparatus and method for efficient data storage using a FIFO memory

Overflow protected first-in first-out architecture

Frequency translation techniques

Systems and methods for implementing a synchronous FIFO with registered outputs

Unsuccessful write retry buffer

Allocating multiple operand data areas of a computer instruction within a program buffer

Adjustable empty threshold limit for a first-in-first-out (FIFO) circuit

Systematic method on queuing of descriptors for multiple flash intelligent DMA engine operation

Sending messages in a network-on-chip and providing a low power state for processing cores

Systems and methods for low interference logging and diagnostics

Rate controlled buffer for output at either a first or second rate responsive to a fill level

Systems and methods for I/O device logging

Flow control for direct memory access transfers

Registered FIFO

Unsuccessful write retry buffer

Synchronizing multicast data distribution on a computing device