189428 ⎘
Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers
EMBEDDING A STATE SPACE MODEL ON MODELS-ON-SILICON HARDWARE ARCHITECTURE
#2ELECTRONIC DEVICE AND METHOD TO REDUCE POWER CONSUMPTION DURING ACCESS
#3BOOSTING LINKED LIST THROUGHPUT
#4MATRIX COMPUTING METHOD, CHIP, AND RELATED DEVICE
#5Multi-input multi-output first-in first-out buffer circuit that reads out multiple data flits at once, and electronic circuits having same
#6Enhanced dynamic random access memory (eDRAM)-based computing-in-memory (CIM) convolutional neural network (CNN) accelerator
#7High-throughput asynchronous data pipeline
#8UART interface circuit and UART data capturing method
#9Arithmetic device and arithmetic circuit for performing multiplication and division
#10Systems and methods for automatic speech recognition based on graphics processing units
#11IC including logic tile, having reconfigurable MAC pipeline, and reconfigurable memory
#12Configurable MAC pipelines for finite-impulse-response filtering, and methods of operating same
#13Performing a top-k function using a binary heap tree
#14Slip detection on multi-lane serial datalinks
#15IC including logic tile, having reconfigurable MAC pipeline, and reconfigurable memory
#16Slip detection on multi-lane serial datalinks
#17Boosting linked list throughput
#18Fixed-point and floating-point arithmetic operator circuits in specialized processing blocks
#19Software-defined device interface system and method
#20Device for neurovascular stimulation
#21Fixed-point and floating-point arithmetic operator circuits in specialized processing blocks
#22Multi-producer single consumer lock-free queues with producer reference counting
#23Fixed-point and floating-point arithmetic operator circuits in specialized processing blocks
#24Work conserving scheduler based on ranking
#25Clock circuit and clock signal transmission method thereof
#26Line-multiplexed UART
#27Self track scheme for multi frequency band serializer de-serializer I/O circuits
#28Flow control with buffer reclamation
#29Resonant inductor coupling clock distribution
#30Lookahead scheme for prioritized reads
#31Boosting linked list throughput
#32Work conserving schedular based on ranking
#33Communication device ingress information management system and method
#34System and method for data synchronization across digital device interfaces
#35S12 TX FIR architecture
#36Data processing
#37Low latency first-in-first-out (FIFO) buffer
#38Method and apparatus for iterative synchronization of two or more electronic devices
#39Crosstalk mitigation in on-chip interfaces
#40Resonant inductor coupling clock distribution
#41Low latency data transfer between clock domains operated in various synchronization modes
#42Accumulation of waveform data using alternating memory banks
#43Waveform accumulation and storage in alternating memory banks
#44BUFFER MANAGEMENT FOR STREAMING DATA
#45Lookahead scheme for prioritized reads
#46FIFO BUFFER AND METHOD OF CONTROLLING FIFO BUFFER
#47Data processing apparatus
#48Method for extracting IBIS simulation model
#49S12 TX FIR architecture
#50Low latency first-in-first-out (FIFO) buffer
#51Multi-level buffering of transactional data
#52Semiconductor memory device
#53Method for processing data using triple buffering
#54Variable-length code (VLC) bitstream parsing in a multi-core processor with buffer overlap regions
#55Decimal computing apparatus, electronic device connectable decimal computing apparatus, arithmetic operation apparatus, arithmetic operation control apparatus, and program-recorded recording medium
#56TD-SCDMA uplink processing
#57Data processing apparatus
#58Multi buffer asynchronous scheme for processing incoming information
#59First-in first-out (FIFO) memory with multi-port functionality
#60Circuitry and methods for efficient FIFO memory
#61Data distribution method and system having a stream buffer device with a sub-buffer table for recording the state of a pluraity of corresponding sub-buffers
#62Method and device for data buffering
#63Decimal computing apparatus, electronic device connectable decimal computing apparatus, arithmetic operation apparatus, arithmetic operation control apparatus, and program-recorded recording medium
#64FIFO memory with single port memory modules for allowing simultaneous read and write operations
#65Hardware architecture for a neural network accelerator
#66Scalable-entry FIFO memory device