189517 ⎘
Methods or arrangements for processing data by operating upon the order or content of the data handled; Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices; Adding; Subtracting; Half or full adders, i.e. basic adder cells for one denomination using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal
ADDING LUT FRACTURABILIY TO FPGA 4-LUTS USING EXISTING ADDER CIRCUITRY
#2LARGE NUMBER INTEGER ADDITION USING VECTOR ACCUMULATION
#3Full adder circuit and multi-bit full adder
#4NEURON CIRCUITS FOR SPIKING NEURAL NETWORKS
#5Split and duplicate ripple circuits
#6Alternative data selector, full adder and ripple carry adder
#7Full adder, chip and computing device
#8ADDING LUT FRACTURABILIY TO FPGA 4-LUTS USING EXISTING ADDER CIRCUITRY
#9Combined SHA2 and SHA3 based XMSS hardware accelerator
#10Novel fast adder
#11Split and duplicate ripple circuits
#12Arithmetic device
#13Adder circuitry for very large integers
#14Full adder circuits with reduced delay
#15Performance power optimized full adder
#16Adder-subtractor circuit and method of controlling adder-subtractor circuit
#17Combined SHA2 and SHA3 based XMSS hardware accelerator
#18Adder circuitry for very large integers
#19Continuous carry-chain packing
#20Prefix network-directed addition
#21Method and system for efficient quantum ternary arithmetic
#22Accumulating data values
#23Adder capable of supporting addition and subtraction of up to n-bit data and method of supporting addition and subtraction of a plurality of data type using the adder
#24Data encryption and decryption with a key by an N-state inverter modified switching function
#25N-state ripple adder scheme coding with corresponding N-state ripple adder scheme decoding
#26Logic module including versatile adder for FPGA
#27N-state ripple adder scheme coding with corresponding n-state ripple adder scheme decoding
#28Carry-ripple adder
#29Electronic circuit with array of programmable logic cells
#30Electronic circuit with array of programmable logic cells
#31Electronic circuit with array of programmable logic cells
#32One bit full adder with sum and carry outputs capable of independent functionalities
#33Apparatus and method for converting, and adder circuit
#34Adder, multiplier and integrated circuit
#35Dual-domain combinational logic circuitry
#36Asynchronous full-adder with majority or minority gates to generate sum true output
#37Ripple carry adder with inverted ferroelectric or paraelectric based adders
#38Dual-domain combinational logic circuitry
#39Compressor, adder circuit and operation method thereof
#40High performance FPGA addition