189538 ⎘
Methods or arrangements for processing data by operating upon the order or content of the data handled; Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices; Multiplying; Dividing; Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with column wise addition of partial products, e.g. using Wallace tree, Dadda counters
Convolution Circuit, Convolution Computing Method, Chip, and Electronic Device
#2IN-MEMORY COMPUTATION CIRCUIT AND METHOD
#3HARDWARE ACCELERATOR WITH MATRIX BLOCK STREAMING
#4MEMORY SYSTEM AND METHODS FOR ACCELERATING RECURRENT NEURAL NETWORKS
#5METHOD FOR PROCESSING DATA USING ADDER AND ELECTRONIC DEVICE
#6Mixed-Radix Multiplier Circuit
#7Multiplier with a new Partial Product Generation Method
#8SYSTEMS AND METHODS FOR DATA PLACEMENT FOR IN-MEMORY-COMPUTE
#9IN-MEMORY COMPUTATION CIRCUIT AND METHOD
#10OPERATION METHOD OF MULTIPLIER, ELECTRONIC DEVICE, AND STORAGE MEDIUM
#11METHODS AND ELECTRONIC DEVICE FOR HIGH PERFORMANCE MODULO MULTIPLICATION
#12MACHINE LEARNING OPTIMIZATION CIRCUIT AND METHOD THEREOF
#13ELECTRO-PHOTONIC NETWORK FOR MACHINE LEARNING
#14Clock signal distribution using photonic fabric
#15ELECTRO-PHOTONIC NETWORK FOR MACHINE LEARNING
#16ACCUMULATOR, MULTIPLIER, AND OPERATOR CIRCUIT
#17HYBRID ELECTRO-PHOTONIC NETWORK-ON-CHIP
#18Systems and methods for data placement for in-memory-compute
#19HARDWARE ACCELERATOR FOR PERFORMING COMPUTATIONS OF DEEP NEURAL NETWORK AND ELECTRONIC DEVICE INCLUDING THE SAME
#20Multi-input configurable logic cell with configurable output region
#21FOLDING COLUMN ADDER ARCHITECTURE FOR DIGITAL COMPUTE IN MEMORY
#22DIGITAL NEURAL NETWORK
#23CLOCK SIGNAL DISTRIBUTION USING PHOTONIC FABRIC
#24Artificial intelligence accelerators
#25COMPUTING APPARATUS AND METHOD FOR VECTOR INNER PRODUCT, AND INTEGRATED CIRCUIT CHIP
#26Compressed wallace trees in FMA circuits
#27Dadda architecture that scales with increasing operand size
#28COMPUTING APPARATUS AND METHOD FOR NEURAL NETWORK OPERATION, INTEGRATED CIRCUIT, AND DEVICE
#29Systems and methods for data placement for in-memory-compute
#30In-memory computation circuit and method
#31Systems and methods for data placement for in-memory-compute
#32Full adder cell with improved power efficiency
#33Full adder cell with improved power efficiency
#34Programmable multiply-add array hardware
#35Semiconductor device including an adder
#36Apparatus and method of fast floating-point adder tree for neural networks
#37Device and method for accelerating matrix multiply operations as a sum of outer products
#38A CALCULATION DEVICE FOR ENCODED ADDITION
#39Apparatus and method for processing an instruction matrix specifying parallel and dependent operations
#40Programmable multiply-add array hardware
#41Apparatus and method for processing an instruction matrix specifying parallel and dependent operations
#42Apparatus and method for processing an instruction matrix specifying parallel and dependent operations
#43Method and apparatus for multiply instructions in data processors
#44Processor executing super instruction matrix with register file configurable for single or multiple threads operations
#45Method and apparatus for performing lossy integer multiplier synthesis
#46System and method of bypassing unrounded results in a multiply-add pipeline unit
#47Reducing power consumption in multi-precision floating point multipliers
#48DELAY OPTIMAL COMPRESSOR TREE SYNTHESIS FOR LUT-BASED FPGAS
#49Adder, Synthesis Device Thereof, Synthesis Method, Synthesis Program, and Synthesis Program Storage Medium
#50Multiplication circuit and de/encryption circuit utilizing the same
#51Floating Point Unit and Cryptographic Unit Having a Shared Multiplier Tree
#52METHOD FOR SIGN-EXTENSION IN A MULTI-PRECISION MULTIPLIER
#53Plural matrices of execution units for processing matrices of row dependent instructions in single clock cycle in super or separate mode
#54Multiplier engine
#55Universal execution unit
#56Converter circuit for converting 1-redundant representation of an integer
#57Multiplication circuitry
#58Multiplication circuitry
#59Carry-ripple adder
#60Combining circuitry
#61Processor core and multiplier that support both vector and single value multiplication
#62Processor core and multiplier that support a multiply and difference operation by inverting sign bits in booth recoding
#63Long-integer multiplier
#64Systolic squarer having five classes of cells
#65Library of low-cost low-power and high-performance multipliers
#66Multiplier with look up tables
#67CSA tree constellation
#68Polynomial and integer multiplication
#69High speed multiplication apparatus of Wallace tree type with high area efficiency
#70Arithmetic unit
#71Adder, multiplier and integrated circuit
#72Multiplier circuit
#73Parallel counter and a logic circuit for performing multiplication