189539 ⎘
Methods or arrangements for processing data by operating upon the order or content of the data handled; Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices; Multiplying; Dividing; Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers
Systems And Methods For Calculating Large Polynomial Multiplications
#2COMPUTATIONAL MEMORY
#3MACHINE LEARNING OPTIMIZATION CIRCUIT AND METHOD THEREOF
#4Multiple Mode Arithmetic Circuit
#5COMPUTER PROCESSOR FOR HIGHER PRECISION COMPUTATIONS USING A MIXED-PRECISION DECOMPOSITION OF OPERATIONS
#6Computational memory
#7MULTIPLE MULTIPLICATION ARRAYS
#8Device and method for accelerating matrix multiply operations
#9Multiple mode arithmetic circuit
#10APPARATUS AND METHOD WITH PARALLEL DATA PROCESSING
#11Computer processor for higher precision computations using a mixed-precision decomposition of operations
#12Multi-partitioning data for combination operations
#13SYSTEMS AND METHODS FOR CALCULATING LARGE POLYNOMIAL MULTIPLICATIONS
#14Computational memory
#15Multiple mode arithmetic circuit
#16Processor with outlier accommodation
#17Method for multiplying polynomials for a cryptographic operation
#18Fast digital multiply-accumulate (MAC) by fast digital multiplication circuit
#19Device and method for accelerating matrix multiply operations
#20Modular gated multiplier circuitry and multiplication technique
#21Computer processor for higher precision computations using a mixed-precision decomposition of operations
#22Computer processor for higher precision computations using a mixed-precision decomposition of operations
#23Arithmetic circuit for performing product-sum arithmetic
#24Multi-partitioning for combination operations
#25Multiple mode arithmetic circuit
#26Computer data processing method and apparatus for large number operations
#27Device and method for accelerating matrix multiply operations as a sum of outer products
#28Device and method for accelerating matrix multiply operations
#29Multiple precision integer multiplier by matrix-matrix multiplications using 16-bit floating point multiplier
#30Methods and instructions for a 32-bit arithmetic support using 16-bit multiply and 32-bit addition
#31Multi-partitioning determination for combination operations
#32Multi-partition operation in combination operations
#33Computer processor for higher precision computations using a mixed-precision decomposition of operations
#34Methods and apparatuses for calculating FP (full precision) and PP (partial precision) values
#35Processor with efficient arithmetic units
#36Device and method for multiplication for impeding side-channel attacks
#37Methods and instructions for 32-bit arithmetic support using 16-bit multiply and 32-bit addition
#38Apparatus and method for controlling operation
#39Vector operations with operand base system conversion and re-conversion
#40Processor with efficient arithmetic units
#41Processor with efficient arithmetic units
#42Large multiplier for programmable logic device
#43Extensible iterative multiplier
#44Fused multiply-adder with booth-encoding
#45Vector multiplication with operand base system conversion and re-conversion
#46SPEED UP BIG-NUMBER MULTIPLICATION USING SINGLE INSTRUCTION MULTIPLE DATA (SIMD) ARCHITECTURES
#47Fused multiply-adder with booth-encoding
#48Method for implementing 32 bit complex multiplication by using 16-bit complex multipliers
#49Processor for performing multiply-add operations on packed data
#50Double-clocked specialized processing block in an integrated circuit device
#51Processor for performing multiply-add operations on packed data
#52Reducing power consumption in multi-precision floating point multipliers
#53Processor and method providing instruction support for instructions that utilize multiple register windows
#54Method and apparatus for performing multiply-add operations on packed data
#55Large multiplier for programmable logic device
#56Multi-phased computational reconfiguration
#57Method and apparatus for providing an area-efficient large unsigned integer multiplier
#58DSP engine with implicit mixed sign operands
#59Digital signal processing circuitry with redundancy and bidirectional data paths
#60Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry
#61SEMICONDUCTOR DEVICE PERFORMING OPERATIONAL PROCESSING
#62Large-factor multiplication in an array of processors
#63Processor for performing multiply-add operations on packed data
#64Method and apparatus for multiplying polynomials with a prime number of terms
#65Reconfigurable arithmetic unit and high-efficiency processor having the same
#66Method and apparatus for calculating a polynomial multiplication, in particular for elliptic curve cryptography
#67MULTIPLICATION CIRCUIT, DIGITAL FILTER, SIGNAL PROCESSING DEVICE, SYNTHESIS DEVICE, SYNTHESIS PROGRAM, AND SYNTHESIS PROGRAM RECORDING MEDIUM
#68Unified integer/galois field (2m) multiplier architecture for elliptic-curve crytpography
#69Unified system architecture for elliptic-curve cryptography
#70Hash function implemention with ROM and CSA
#71MULTIPLY AND MULTIPLY AND ACCUMULATE UNIT
#72Bandwidth efficient instruction-driven multiplication engine
#73Multiplier
#74Large multiplier for programmable logic device
#75Reconfigurable SIMD vector processing system
#76Parameterized VLSI Architecture And Method For Binary Multipliers
#77Device and method for calculating a result of a modular multiplication with a calculating unit smaller than the operands
#78Method of Performing a Modular Multiplication and Method of Performing a Euclidean Multiplication Using Numbers with 2N Bits
#79Systems and Methods for Implementing a Double Precision Arithmetic Memory Architecture
#80System, method and apparatus for multiplying large numbers in a single iteration using graphs
#81Multiplying two numbers
#82Modular binary multiplier for signed and unsigned operands of variable widths
#83Scalable, faster method and apparatus for montgomery multiplication
#84Modular binary multiplier for signed and unsigned operands of variable widths
#85Programmable processing unit providing concurrent datapath operation of multiple instructions
#86Programmable processing unit with an input buffer and output buffer configured to exclusively exchange data with either a shared memory logic or a multiplier based upon a mode instruction
#87Device and method for calculating a multiplication addition operation and for calculating a result of a modular multiplication
#88Karatsuba based multiplier and method
#89Long-integer multiplier
#90Method and apparatus for arithmatic operation of processor
#91Apparatus and method of multiplication using a plurality of identical partial multiplication modules
#92Apparatus and method for calculating a result of a modular multiplication
#93Split radix multiplication
#94Method and system for high performance, multiple-precision multiply-and-add operation
#95Data format suitable for fast massively parallel general matrix multiplication in a programmable IC
#96Low power optimizations for a floating point multiplier
#97Large multiplier for programmable logic device
#98Systems and methods for DSP block enhancement
#99Ternary DSP block
#100Signed multiplier circuit utilizing a uniform array of logic blocks
#101Multiplier circuits with optional shift function