ClassID:

189563

G06F7/607 - CPC Classification

Classification description:

Methods or arrangements for processing data by operating upon the order or content of the data handled; Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers number-of-ones counters, i.e. devices for counting the number of input lines set to ONE among a plurality of input lines, also called bit counters or parallel counters

Recent Application in this class:
#1
20240176846
2024-05-30

STOCHASTIC COMPUTING WITH GENERATED DETERMINISTIC SEQUENCES

#2
20230418606
2023-12-28

Vector population count determination via comparison iterations in memory

#3
20220345135
2022-10-27

Monotonic counter memory system

#4
20210132946
2021-05-06

Vector population count determination via comparsion iterations in memory

#5
20210041905
2021-02-11

Digital circuit to detect presence and quality of an external timing device

#6
20200371806
2020-11-26

Statistical mode determination

#7
20200293283
2020-09-17

Programmable multiply-add array hardware

#8
20200264842
2020-08-20

Performing processing using hardware counters in a computer system

#9
20190196788
2019-06-27

Programmable multiply-add array hardware

#10
20190102172
2019-04-04

Vector population count determination via comparison iterations in memory

#11
20180062664
2018-03-01

Carry-less population count

#12
20160313975
2016-10-27

Multi-bit full adder based on resistive-switching devices and operation methods thereof

#13
20160266899
2016-09-15

Vector population count determination in memory

#14
20140189307
2014-07-03

Vector address conflict resolution with vector population count functionality

#15
20130054504
2013-02-28

Method of pattern recognition for artificial intelligence

#16
20120265793
2012-10-18

MERGED COMPRESSOR FLOP CIRCUIT

#17
20120230460
2012-09-13

Method to implement a monotonic counter with reduced flash part wear

#18
20110238717
2011-09-29

Linear bit counting implementations

#19
20110102453
2011-05-05

Image Processing Device with a CSA Accumulator for Improving Image Quality and Related Method

#20
20100082718
2010-04-01

Combined set bit count and detector logic

#21
20100042806
2010-02-18

Determining index values for bits of binary vector by processing masked sub-vector index values

#22
20090259877
2009-10-15

Method to implement a monotonic counter with reduced flash part wear

#23
20090216826
2009-08-27

Generalized programmable counter arrays

#24
20090077286
2009-03-19

Data bus inversion detection mechanism

#25
20090063609
2009-03-05

Static 4:2 Compressor with Fast Sum and Carryout

#26
20090019100
2009-01-15

Population count approximation circuit and method thereof

#27
20090016480
2009-01-15

Circuit and method for correlated inputs to a population count circuit

#28
20080282136
2008-11-13

Parity generation circuit, counter circuit, and counting method

#29
20080147954
2008-06-19

Crossbar arithmetic and summation processor

#30
20080052611
2008-02-28

CSA 5-3 compressor circuit and carry-save adder circuit using same

#31
20070233761
2007-10-04

Crossbar arithmetic processor

#32
20070211316
2007-09-13

Image processing device with a CSA accumulator for improving image quality and related method

#33
20070198619
2007-08-23

Reconfigurable circuit

#34
20060294178
2006-12-28

Carry-ripple adder

#35
20060242221
2006-10-26

Data value addition

#36
20060020655
2006-01-26

Library of low-cost low-power and high-performance multipliers

#37
20050259502
2005-11-24

Parallel processing device and parallel processing method

#38
20050240646
2005-10-27

Reconfigurable matrix multiplier architecture and extended borrow parallel counter and small-multiplier circuits

#39
20050165878
2005-07-28

4:2 Carry save adder and 4:2 carry save adding method

#40
20050114424
2005-05-26

Multibit bit adder

#41
20050102346
2005-05-12

Computing carry-in bit to most significant bit carry save adder in current stage

#42
20050102345
2005-05-12

4-to-2 carry save adder using limited switching dynamic logic

#43
20050071416
2005-03-31

Low-power high-speed 4-2 compressor with minimized transistor count

#44
20050044125
2005-02-24

4-2 Compressor

#45
20050027777
2005-02-03

High speed low power 4-2 compressor

#46
20050021585
2005-01-27

Parallel counter and a logic circuit for performing multiplication

#47
20050017878
2005-01-27

Serial weightless data to thermometer coded data converter