189579 ⎘
Methods or arrangements for processing data by operating upon the order or content of the data handled Selecting or encoding within a word the position of one or more bits having a specified value, e.g. most or least significant one or zero detection, priority encoders
ENHANCED INTEGER ENCODING FOR ARITHMETIC PROCESSORS
#2INSERTING PREDEFINED PAD VALUES INTO A STREAM OF VECTORS
#3DATA ENCODING AND DECODING SCHEMES
#4IMPROVED TRANSFORMERS USING FAITHFUL POSITIONAL ENCODING
#5ZERO-DETECTION FOR LOGIC CIRCUIT MULTIPLICATION
#6OPTIMIZING METHOD AND COMPUTING SYSTEM FOR DEEP LEARNING NETWORK
#7EFFICIENT COMPUTATION OF A SHARED EXPONENT
#8Inserting predefined pad values into a stream of vectors
#9APPARATUS AND METHOD WITH DATA PROCESSING
#10ARTIFICIAL INTELLIGENCE ACCELERATORS
#11EFFICIENT COMPUTATION OF A SHARED EXPONENT
#12Compression of data that exhibits mixed compressibility
#13HARDWARE ACCELERATOR FOR FLOATING-POINT OPERATIONS
#14SIGNAL PROCESSING SYSTEM FOR PERFORMING A FAST FOURIER TRANSFORM WITH ADAPTIVE BIT SHIFTING, AND METHODS FOR ADAPTIVE BIT SHIFTING
#15SECRET MSB NORMALIZATION SYSTEM, DISTRIBUTED PROCESSING APPARATUS, SECRET MSB NORMALIZATION METHOD, PROGRAM
#16Verifying the correctness of a leading zero counter
#17Rounding hexadecimal floating point numbers using binary incrementors
#18Trailing or leading digit anticipator
#19In-memory bit-serial addition system
#20FIND FIRST FUNCTION
#21Method and apparatus with neural network convolution operations
#22CONSTANT MULTIPLICATION BY DIVISION
#23Finite State Machine-Based Bit-Stream Generator for Low-Discrepancy Stochastic Computing
#24DIGIT-RECURRENCE SELECTION CONSTANTS
#25Sum address memory decoded dual-read select register file
#26Compression of data that exhibits mixed compressibility
#27METHOD AND APPARATUS WITH DATA PROCESSING
#28Storage medium and operation device handling an alternative floating-point format
#29In-memory computing method and in-memory computing apparatus
#30Inserting predefined pad values into a stream of vectors
#31Display panel driver, source driver, and display device including the source driver
#32Electronic device performing outlier-aware approximation coding and method thereof
#33Compression and decompression engines and compressed domain processors
#34Partially and fully parallel normaliser
#35Trailing or leading digit anticipator
#36Data processing system configured for separated computations for positive and negative data
#37Layout pattern of two-port ternary content addressable memory
#38In-memory bit-serial addition system
#39Method and apparatus with data processing
#40Two-port ternary content addressable memory and layout pattern thereof, and associated memory device
#41Compression and decompression engines and compressed domain processors
#42Partially and fully parallel normaliser
#43METHODS AND APPARATUSES FOR CACHELINE CONSCIOUS EXTENDIBLE HASHING
#44Method and apparatus with neural network convolution operations
#45Trailing or leading digit anticipator
#46Computer data processing method and apparatus for large number operations
#47Decimal load immediate instruction
#48Compression and decompression engines and compressed domain processors
#49Apparatuses for integrating arithmetic with logic operations
#50Trailing or leading digit anticipator
#51Inserting predefined pad values into a stream of vectors
#52Partially and fully parallel normaliser
#53Trailing or leading digit anticipator
#54Compression and decompression engines and compressed domain processors
#55Apparatuses for integrating arithmetic with logic operations
#56Trailing or leading zero counter having parallel and combinational logic
#57Zero detection of a sum of inputs without performing an addition
#58Leading zero anticipation
#59Decimal load immediate instruction
#60Decimal load immediate instruction
#61Trailing or leading zero counter having parallel and combinational logic
#62Direct memory access transmission control method and apparatus
#63Partially and fully parallel normaliser
#64Data extraction method and apparatus
#65Trailing or leading zero counter having parallel and combinational logic
#66Trailing or leading digit anticipator
#67Floating point computation apparatus and method
#68Trailing or leading zero counter having parallel and combinational logic
#69Data processing apparatus and method for performing a shift function on a binary number
#70Comparing a runlength of bits with a variable number
#71Trailing or leading zero counter having parallel and combinational logic
#72Partially and fully parallel normaliser
#73Digest obfuscation for data cryptography
#74Multiplier circuit
#75Hybrid dynamic-static encoder with optional hit and/or multi-hit detection
#76Longest prefix match internet protocol content addressable memories and related methods
#77Leading change anticipator logic
#78Half width counting leading zero circuit using comparators
#79Multi-priority encoder
#80Programmable priority encoder
#81Apparatus and method for performing floating point addition
#82Method and apparatus for calculating the number of leading zero bits of a binary operation
#83Mechanism to find first two values
#84Longest prefix match internet protocol content addressable memories and related methods
#85Multi-priority encoder
#86Low depth programmable priority encoders
#87Decimal floating-point adder with leading zero anticipation
#88Low depth programmable priority encoders
#89Combined set bit count and detector logic
#90Normalizer shift prediction for log estimate instructions
#91Leading zero estimation modification for unfused rounding catastrophic cancellation
#92Priority encoder
#93Processor and method of determining a normalization count
#94Efficient leading zero anticipator
#95Low-power content-addressable-memory device
#96Data correction circuit
#97Half width counting leading zero circuit
#98Content addressable memory address resolver
#99Redundancy-free circuits for zero counters
#100Content addressable memory
#101Parity generator, priority encoder, and information processor
#102System and method for detecting multiple matches
#103Fast sparse list walker
#104High performance renormalization for binary arithmetic video coding
#105Multiplier product generation based on encoded data from addressable location
#106Physical priority encoder
#107Arithmetic operation unit, information processing apparatus and arithmetic operation method
#108Asynchronous signed multiplier and algorithm thereof
#109Leading-Zero Counter and Method to Count Leading Zeros
#110Apparatus and methods for a static mux-based priority encoder
#111Method and system for high-speed floating-point operations and related computer program product
#112System and method of counting leading zeros and counting leading ones in a digital signal processor
#113Redundancy-free circuits for zero counters
#114Physical priority encoder
#115Low power content-addressable-memory device
#116Data converter and a delay threshold comparator
#117Zero detect in partial sums while adding
#118System and method for reduction of leading zero detect for decimal floating point numbers
#119Leading zero counter for binary data alignment
#120Construction of a folded leading zero anticipator
#121Efficient execution and emulation of bit scan operations
#122Method and apparatus to correct leading one prediction
#123Hit ahead hierarchical scalable priority encoding logic and circuits
#124High performance implementation of exponent adjustment in a floating point design
#125Priority circuit
#126Stable variable-length order-preserving encoding scheme
#127Storing data items with content encoded in storage addresses