189581 ⎘
Methods or arrangements for processing data by operating upon the order or content of the data handled; Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data having at least two separately controlled rearrangement levels, e.g. multistage interconnection networks
SPARSE COMPUTE-IN-MEMORY TENSOR CORE
#2SYSTEMS, METHODS, AND APPARATUSES FOR TILE MATRIX MULTIPLICATION AND ACCUMULATION
#3SYSTEMS, METHODS, AND APPARATUSES FOR TILE TRANSPOSE
#4SYSTEMS, METHODS, AND APPARATUSES FOR TILE LOAD
#5SYSTEMS, METHODS, AND APPPARATUS FOR MATRIX MOVE
#6SYSTEMS, METHODS, AND APPARATUSES FOR TILE STORE
#7SYSTEMS, METHODS, AND APPARATUSES FOR MATRIX OPERATIONS
#8SYSTEMS, METHODS, AND APPARATUSES FOR MATRIX ADD, SUBTRACT, AND MULTIPLY
#9Systems, methods, and apparatus for tile configuration
#10Systems, methods, and apparatuses for tile load, multiplication and accumulation
#11SYSTEMS, METHODS, AND APPARATUSES FOR ZEROING A MATRIX
#12Systems, methods, and apparatuses for tile store
#13Systems, methods, and apparatuses for tile store
#14Neural network operation method and apparatus with mapping orders
#15Systems, methods, and apparatus for matrix move
#16Tiled Switch Matrix Data Permutation Circuit
#17Systems, methods, and apparatuses for matrix add, subtract, and multiply
#18Systems, methods, and apparatuses for dot production operations
#19Systems, methods, and apparatus for tile configuration
#20Systems, methods, and apparatuses for tile matrix multiplication and accumulation
#21Systems, methods, and apparatuses for dot production operations
#22Tiled switch matrix data permutation circuit
#23Pair merge execution units for microinstructions
#24Systems, methods, and apparatuses for tile load
#25Systems, methods, and apparatuses for tile broadcast
#26Systems, methods, and apparatus for tile configuration
#27Systems, methods, and apparatuses for zeroing a matrix
#28Systems, methods, and apparatuses for tile matrix multiplication and accumulation
#29Systems, methods, and apparatuses for tile store
#30Systems, methods, and apparatus for matrix move
#31Tiled switch matrix data permutation circuit
#32Systems, methods, and apparatuses for matrix operations
#33Systems, methods, and apparatuses for matrix add, subtract, and multiply
#34Systems, methods, and apparatuses for tile transpose
#35Systems, methods, and apparatuses for tile diagonal
#36Multi-packet processing with ordering rule enforcement
#37Parallel bit reversal devices and methods
#38Microprocessor Shifter Circuits Utilizing Butterfly and Inverse Butterfly Routing Circuits, and Control Circuits Therefor
#39Data Shifter and Control Method Thereof, Multiplexer, Data Sifter, and Data Sorter
#40Data rearranging circuit, variable delay circuit, fast fourier transform circuit, and data rearranging method
#41Cyclic shift device, cyclic shift method, LDPC decoding device, television receiver, and reception system
#42Electronic device, barrel shifter unit and method of barrel shifting
#43Method and apparatus for correlation of intersections of network resources
#44Method and system for a wiring-efficient permute unit
#45Microprocessor shifter circuits utilizing butterfly and inverse butterfly routing circuits, and control circuits therefor
#46Data processing apparatus
#47ELECTRONIC DATA SHIFT DEVICE, IN PARTICULAR FOR CODING/DECODING WITH AN LDPC CODE
#48Digital electronic binary rotator and reverser
#49System, apparatus and method for data path routing configurable to perform dynamic bit permutations
#50Method and apparatus for providing packed shift operations in a processor
#51Rotator/shifter arrangement
#52Area efficient shift / rotate system
#53Method and apparatus for providing packed shift operations in a processor
#54Techniques for transposition of a matrix arranged in a memory as multiple items per word
#55Method and apparatus for providing packed shift operations in a processor
#56Multiplexing operations in SIMD processing
#57Method and system for performing permutations with bit permutation instructions
#58Hardware-efficient implementation of dynamic element matching in sigma-delta DAC's
#59Data-transfer test mode