189582 ⎘
Methods or arrangements for processing data by operating upon the order or content of the data handled; Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data Masking
PROCESSOR
#2DYNAMIC ELEMENT MATCHING ENCODER PROVIDING A QUASI-CONSTANT NUMBER OF TRANSITIONS AS A FUNCTION OF A CONTROL WORD
#3Security Device
#4PROCESSING NON-POWER-OF-TWO WORK UNIT IN NEURAL PROCESSOR CIRCUIT
#5TECHNIQUE FOR GENERATING AN OUTPUT VALUE REPRESENTING A SHIFTED INPUT VALUE
#6DEVICE AND METHODS FOR FUNCTIONAL DESCRIPTOR-BASED DMA CONTROLLER
#7METHOD FOR SELECTING A VALUE AMONGST TWO VALUES RECORDED IN TWO DIFFERENT REGISTERS
#8METHOD FOR CALCULATING A TRANSITION FROM A BOOLEAN MASKING TO AN ARITHMETIC MASKING
#9SECURE COMPUTATION SYSTEM, SECURE COMPUTATION SERVER APPARATUS, SECURE COMPUTATION METHOD, AND SECURE COMPUTATION PROGRAM
#10CHARACTER RECOGNITION MODEL TRAINING METHOD AND APPARATUS, CHARACTER RECOGNITION METHOD AND APPARATUS, DEVICE AND STORAGE MEDIUM
#11Carry-lookahead adder, secure adder and method for performing carry-lookahead addition
#12PARALLEL COMPUTATION OF A LOGIC OPERATION, INCREMENT, AND DECREMENT OF ANY PORTION OF A SUM
#13MULTIPLICATION
#14MASKED SHIFTED ADD OPERATION
#15COMBINED DIVIDE/SQUARE ROOT PROCESSING CIRCUITRY AND METHOD
#16Masked decoding of polynomials
#17CROSS-DOMAIN ADAPTIVE LEARNING
#18PROCESSING NON-POWER-OF-TWO WORK UNIT IN NEURAL PROCESSOR CIRCUIT
#19CAN filter combining method, device, and CAN controller
#20Data processing device and method for the cryptographic processing of data
#21Information processing apparatus, secure computation method, and program
#22Method for performing cryptographic operations on data in a processing device, corresponding processing device and computer program product
#23Converting a boolean masked value to an arithmetically masked value for cryptographic operations
#24Protection system and method
#25Circuit and method for binary flag determination
#26DEVICE AND METHOD FOR EXTRACTION AND INSERTION OF BINARY WORDS
#27Processor and method for processing mask data
#28Computation device and method
#29Snapping experience with clipping masks
#30Method for securing a cryptographic process with SBOX against high-order side-channel attacks
#31Physically unclonable function device with a load circuit to generate bias to sense amplifier
#32METHOD AND APPARATUS FOR PERFORMING A VECTOR PERMUTE WITH AN INDEX AND AN IMMEDIATE
#33CONTROLLING ACCESS TO DATA IN A DATABASE BASED ON DENSITY OF SENSITIVE DATA IN THE DATABASE
#34ARITHMETIC PROCESSING DEVICE, IMAGE PROCESSING DEVICE, AND IMAGING DEVICE
#35Statistical object generator
#36Converting a boolean masked value to an arithmetically masked value for cryptographic operations
#37Zero coefficient skipping convolution neural network engine
#38Data processing apparatus and method for processing a SIMD instruction specifying a control value having a first portion identifying a selected data size and a second portion identifying at least one control parameter having a number of bits that varies in dependence on a number of bits comprised by the first portion
#39Multi-element instruction with different read and write masks
#40NEURAL NETWORK SUPPRESSION
#41Information processing device, and control method and storage medium
#42Method and apparatus for performing a vector permute with an index and an immediate
#43Apparatus and method including an instruction for performing a logical operation on a repeating data value generated based on data size and control parameter portions specified by the instruction
#44Floating mask generation for network packet flow
#45System and method for reducing memory I/O power via data masking
#46Fused multiply add operations using bit masks
#47Method and system for protecting execution of cryptographic hash functions
#48Identifier selection
#49METHOD AND APPARATUS FOR PROCESSING MASKED DATA
#50Multi-element instruction with different read and write masks
#51Semiconductor device and method of generating random data
#52Apparatus and method for processing a bitfield manipulation instruction having a control value indicating insertion or extraction form
#53Configurable status processing unit for sensor-actuator systems
#54Operation unit and program
#55Function securing unit for communication systems
#56Method and system for logical data masking
#57Identifier selection
#58Inclusive “OR” bit matrix compare resolution of vector update conflict masks
#59STANDARD CELL FOR ARITHMETIC LOGIC UNIT AND CHIP CARD CONTROLLER
#60Circuit and method converting boolean and arithmetic masks
#61Method and related device for hardware-oriented conversion between arithmetic and boolean random masking
#62Intentionally delaying execution of a copy instruction to achieve simultaneous execution with a subsequent, non-adjacent write instruction
#63Runtime loading of configuration data in a configurable IC
#64Configurable IC with packet switch network
#65Standard cell for arithmetic logic unit and chip card controller
#66Bit field operation circuit
#67Standard cell for arithmetic logic unit and chip card controller
#68Fast rotator with embedded masking and method therefor
#69Method and apparatus for producing an index vector for use in performing a vector permute operation
#70Vectorized table lookup
#71Bit field extraction with sign or zero extend
#72Retrieving multi-byte vector elements from byte indexed table using replicated and consecutive number added indices for each element index
#73Validating a variable data item in a software routine
#74Computer processing system and method configured to effectuate lower-order masking in a higher-order masked design
#75Reducing power consumption in integrated circuits
#76Security system using keys encoded in holograms