189584 ⎘
Methods or arrangements for processing data by operating upon the order or content of the data handled; Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data Data position reversal, e.g. bit reversal, byte swapping
FFT ENGINE HAVING COMBINED BIT-REVERSAL AND MEMORY TRANSPOSE OPERATIONS
#2METHOD AND SYSTEM FOR REMOVING NOISE FROM DIGITAL DATA
#3CONSTANT MODULO VIA RECIRCULANT REDUCTION
#4COMPUTE ENGINE WITH TRANSPOSE CIRCUITRY
#5COMPUTATION METHOD AND COMPUTATION APPARATUS WITH INPUT SWAPPING
#6HARDWARE-BASED GALOIS MULTIPLICATION
#7FFT ENGINE HAVING COMBINED BIT-REVERSAL AND MEMORY TRANSPOSE OPERATIONS
#8SYSTEMS AND METHODS FOR DECOMPOSED DIGITAL FILTER
#9MICROPROCESSOR EQUIPPED WITH AN ARITHMETIC AND LOGIC UNIT AND WITH A HARDWARE SECURITY MODULE
#10Tiled Switch Matrix Data Permutation Circuit
#11CRYPTOGRAPHIC ARCHITECTURE FOR CRYPTOGRAPHIC PERMUTATION
#12Cryptography using a cryptographic state
#13SYSTEM AND CONTROL DEVICE
#14In-memory computing method and apparatus
#15Secure joining system, method, secure computing apparatus and program
#16Method for performing cryptographic operations on data in a processing device, corresponding processing device and computer program product
#17FFT engine having combined bit-reversal and memory transpose operations
#18Information processing device, information processing system, and non-transitory computer-readable storage medium for storing program
#19Processor memory optimization method and apparatus for deep learning training tasks
#20Transposing in a matrix-vector processor
#21Secure aggregate order system, secure computation apparatus, secure aggregate order method, and program
#22Tiled switch matrix data permutation circuit
#23Matrix normal/transpose read and a reconfigurable data processor including same
#24FFT engine having combined bit-reversal and memory transpose operations
#25Audio signal circuit with in-place bit-reversal
#26Tiled switch matrix data permutation circuit
#27Transposing in a matrix-vector processor
#28Method and apparatus for frequency interleaving
#29Transposing in a matrix-vector processor
#30Layered vector architecture compatibility for cross-system portability
#31Semiconductor device and data processing system selectively operating as one of a big endian or little endian system
#32Wear leveling in non-volatile memories
#33Wear leveling in non-volatile memories
#34Access network for address mapping in non-volatile memories
#35Data processing apparatus and method for processing a SIMD instruction specifying a control value having a first portion identifying a selected data size and a second portion identifying at least one control parameter having a number of bits that varies in dependence on a number of bits comprised by the first portion
#36Semiconductor device and data processing system selectively operating as one of a big endian or little endian system
#37Semiconductor device and data processing system selectively operating as one of a big endian or little endian system
#38Layered vector architecture compatibility for cross-system portability
#39Compiler optimizations for vector instructions
#40Layered vector architecture compatibility for cross-system portability
#41Compiler optimizations for vector instructions
#42Apparatus and method including an instruction for performing a logical operation on a repeating data value generated based on data size and control parameter portions specified by the instruction
#43Semiconductor device and data processing system selectively operating as one of a big endian or little endian system
#44Semiconductor device and data processing system selectively operating as one of a big endian or little endian system
#45Method and apparatus for frequency interleaving
#46Parallel bit reversal devices and methods
#47Endian conversion method and system
#48Semiconductor device and data processing system selectively operating as one of a big endian or little endian system
#49Semiconductor device and data processing system selectively operating as one of a big endian or little endian system
#50Apparatus and method for processing a bitfield manipulation instruction having a control value indicating insertion or extraction form
#51Method and system for logical data masking
#52SELECTOR CIRCUIT
#53Semiconductor device and data processing system selectively operating as one of a big endian or little endian system
#54Efficient transfer of matrices for matrix based operations
#55Semiconductor device and data processing system selectively operating as one of a big endian or little endian system
#56System and method to perform fast rotation operations
#57INFORMATION APPARATUS
#58Data processing apparatus and data processing method
#59Data processing apparatus
#60Apparatus and method for performing rearrangement and arithmetic operations on data
#61Digital electronic binary rotator and reverser
#62System, apparatus and method for data path routing configurable to perform dynamic bit permutations
#63Permutable address processor and method
#64Data conversion method and client-server system
#65Fast rotator with embedded masking and method therefor
#66Semiconductor device and data processing system selectively operating as one of a big endian or little endian system
#67Area efficient shift / rotate system
#68Multiplexing operations in SIMD processing
#69Endianess compensation within a SIMD data processing system
#70Endian conversion
#71Transposing in a matrix-vector processor