189620 ⎘
Arrangements for software engineering; Transformation of program code; Compilation; Encoding Register allocation; Assignment of physical memory space to logical memory space
ADDRESS GENERATION FOR A FRACTURABLE DATAPATH IN A RECONFIGURABLE DATA PROCESSOR
#2LOOP POINTERS FOR RECURSIVE TO ITERATIVE TRANSFORMATION
#3INDEPENDENT ADDRESS SEQUENCE GENERATION FOR A COARSE-GRAINED RECONFIGURABLE PROCESSOR
#4CONSTANT MEMORY SEGMENTATION FOR PARALLEL PROCESSORS
#5COMPILER SYMBOL TABLE SUPPORT TO AVOID PRIVATE MEMORY SPILLS FOR TEMPORARY ARRAY ACCESSES
#6COMPILER-BASED SYNCHRONIZATION FOR DATAFLOW GRAPHS ON COARSE-GRAINED RECONFIGURABLE ARCHITECTURES
#7Interoperable Composite Data Units for use in Distributed Computing Execution Environments
#8HETEROGENEOUS FUNCTIONAL PROCESSING ARCHITECTURES AND METHODS TO DESIGN AND FABRICATE THE SAME
#9Interoperable Composite Data Units for use in Distributed Computing Execution Environments
#10COMPILED SHADER PROGRAM CACHES IN A CLOUD COMPUTING ENVIRONMENT
#11Live Range Reduction to Enhance Register Allocation of Structured Control Flow Programs
#12Interoperable composite data units for use in distributed computing execution environments
#13Interoperable composite data units for use in distributed computing execution environments
#14FIRMWARE EVENT STACK ROUTING
#15COMPILATION TECHNIQUE USING METRICS
#16CONSTANT MEMORY SEGMENTATION FOR PARALLEL PROCESSORS
#17Optimization of Scratchpad Memory Allocation for Heterogeneous Devices Using A Cooperative Compiler Framework
#18Interoperable composite data units for use in distributed computing execution environments
#19Configuration File Generation For Fracturable Data Path In A Coarse-Grained Reconfigurable Processor
#20Optimization of Scratchpad Memory Allocation for Heterogeneous Devices Using A Cooperative Compiler Framework
#21Space- And Time-Efficient Enumerations
#22Embedding code from modules across versioning boundaries
#23TECHNOLOGIES FOR UNTRUSTED CODE EXECUTION WITH PROCESSOR SANDBOX SUPPORT
#24COMMON PARSER-DEPARSER FOR LIBRARIES OF PACKET-PROCESSING PROGRAMS
#25Interoperable composite data units for use in distributed computing execution environments
#26Space- and time-efficient enumerations
#27Deterministic memory allocation for real-time applications
#28Configurable Access to a Multi-Die Reconfigurable Processor by a Virtual Function
#29Handling Interrupts from a Virtual Function in a System with a Multi-Die Reconfigurable Processor
#30Handling Interrupts from a Virtual Function in a System with a Reconfigurable Processor
#31Configurable Access to a Reconfigurable Processor by a Virtual Function
#32Concept for Handling Memory Spills
#33CODE PROCESSING METHOD, APPARATUS, AND DEVICE
#34Fracturable data path in a reconfigurable data processor
#35Compiler for a fracturable data path in a reconfigurable data processor
#36COMPILER-BASED INPUT SYNCHRONIZATION FOR PROCESSOR WITH VARIANT STAGE LATENCIES
#37Partitioning and parallel loading of property graphs with constraints
#38Compiled shader program caches in a cloud computing environment
#39Methods and devices for computing a memory size for software optimization
#40Interoperable composite data units for use in distributed computing execution environments
#41System and method for responsive process security classification and optimization
#42SYSTEMS AND METHODS FOR REDUCING REGISTER BANK CONFLICTS BASED ON SOFTWARE HINT AND HARDWARE THREAD SWITCH
#43Technologies for untrusted code execution with processor sandbox support
#44Compiler for RISC processor having specialized registers
#45Systems and methods for extending a live range of a virtual scalar register
#46Method and system for optimizing access to constant memory
#47Electronic device and control method thereof
#48VIRTUAL REGISTER FILE
#49Context switching locations for compiler-assisted context switching
#50Delegating bytecode runtime compilation to serverless environment
#51Compiler operations for heterogeneous code objects
#52Pre-instruction scheduling rematerialization for register pressure reduction
#53Executing a part of a compiler generated code as a function
#54Bindpoint emulation
#55Multi-thread processing
#56Large lookup tables for an image processor
#57Automatic generation of efficient vector code with low overhead in a time-efficient manner independent of vector width
#58Register sharing mechanism to equally allocate disabled thread registers to active threads
#59Compiler and information processing method for deleting spill instructions
#60Compiler-optimized context switching with compiler-inserted data table for in-use register identification at a preferred preemption point
#61Program conversion device, program conversion method, and non-transitory recording medium having program conversion program recorded therein
#62Dynamic memory protection
#63Memory pool allocation for a multi-core system
#64Compiler for translating between a virtual image processor instruction set architecture (ISA) and target hardware having a two-dimensional shift array structure
#65Method for executing a program in a computer
#66System and method for high throughput in multiple computations
#67Dynamic memory protection
#68Generating code for function calls that use multiple addressing modes
#69Generating code for function calls that use multiple addressing modes
#70Function evaluation using multiple values loaded into registers by a single instruction
#71Recompiling GPU code based on spill/fill instructions and number of stall cycles
#72Processor that includes a special store instruction used in regions of a computer program where memory aliasing may occur
#73Memory pool allocation for a multi-core system
#74Systems and methods for reducing register bank conflicts based on a software hint bit causing a hardware thread switch
#75Virtual address table
#76Executing short pointer mode applications loaded in a memory address space having one portion addressable by short pointers and a shadow copy of the one portion
#77Compiler for a processor comprising primary and non-primary functional units
#78Compiler for a processor comprising primary and non-primary functional units
#79CONDITIONAL STACK FRAME ALLOCATION
#80Technologies for untrusted code execution with processor sandbox support
#81Supporting compiler variable instrumentation for uninitialized memory references
#82Latency measurement technology
#83Techniques for compiler sheltered non-volatile memory stores
#84Compiler for translating between a virtual image processor instruction set architecture (ISA) and target hardware having a two-dimensional shift array structure
#85Reconfiguration of address space based on loading short pointer mode application
#86Automatic program synthesis using monadic second-order logic
#87Virtual register file
#88Virtual address table
#89General purpose register allocation in streaming processor
#90Comparisons in function pointer localization
#91Comparisons in function pointer localization
#92Reconfiguration of address space based on loading short pointer mode application
#93Processor that includes a special store instruction used in regions of a computer program where memory aliasing may occur
#94System and method for partition administrative targeting in an application server environment
#95Detecting sequential access data and random access data for placement on hybrid main memory for in-memory databases
#96Application Code Hiding Apparatus by Modifying Code in Memory and Method of Hiding Application Code Using the Same
#97Systems and methods for using error correction and pipelining techniques for an access triggered computer architecture
#98Relaxing user-specified register constraints for improving register allocation
#99Compiler for translating between a virtual image processor instruction set architecture (ISA) and target hardware having a two-dimensional shift array structure
#100Input/output (I/O) binding with automatic international electromechanical commission (IEC) address generation in remote terminal unit (RTU) configuration
#101Automation device processor and method for operating the automation device
#102System and method for modulo addressing vectorization with invariant code motion
#103Conditional stack frame allocation
#104Conditional stack frame allocation
#105Register spill management for general purpose registers (GPRs)
#106Allocation method, apparatus, and program for managing architectural registers and physical registers using mapping tables
#107Advanced interactive command-line front-end for graph analysis systems
#108Compiler for translating between a virtual image processor instruction set architecture (ISA) and target hardware having a two-dimensional shift array structure
#109Virtual register file
#110Method and apparatus for performing register allocation
#111Processor and command processing method performed by same
#112Efficient error handling mechanisms in data storage systems
#113Skipping of data storage
#114Virtual address table
#115Register liveness analysis for SIMD architectures
#116Register allocation for vectors
#117Efficient error handling mechanisms in data storage systems
#118Systems and methods for register allocation
#119Allocation of alias registers in a pipelined schedule
#120Method and system for compiler optimization
#121Allocation method, apparatus, and program for managing architectural registers and physical registers using mapping tables
#122Method of compilation, computer program and computing system
#123Method and apparatus for code size reduction
#124Code generation using data marking
#125Method and apparatus for dynamic data configuration
#126GENERATING OBJECT CODE FROM A CONJOINED ASSEMBLER DIRECTIVE
#127Profile-based global live-range splitting
#128Profile-based global live-range splitting
#129Method and apparatus for avoiding register interference
#130Method and apparatus for register spill minimization
#131Multi-core processor system, synchronization control system, synchronization control apparatus, information generating method, and computer product
#132Optimization method for compiler, optimizer for a compiler and storage medium storing optimizing code
#133Compiler for providing intrinsic supports for VLIW PAC processors with distributed register files and method thereof
#134Processing vectors using a wrapping rotate previous instruction in the macroscalar architecture
#135Creating multiple versions for interior pointers and alignment of an array
#136Using range validation in assembly language programming
#137Register liveness analysis for SIMD architectures
#138Register allocation for graphics processing
#139Macroscalar processor architecture
#140Macroscalar processor architecture
#141Allocating register halves independently
#142Path-sensitive analysis for reducing rollback overheads
#143Register mapping techniques for efficient dynamic binary translation
#144Translation of register-combiner state into shader microcode
#145Register allocation with SIMD architecture using write masks
#146LANGUAGE PROCESSING APPARATUS, LANGUAGE PROCESSING METHOD, AND COMPUTER PROGRAM PRODUCT
#147Minimizing register spills by using register moves
#148Register prespill phase in a compiler
#149Eliminating redundant operations for common properties using shared real registers
#150Macroscalar processor architecture
#151Intermediate form for bitwidth sensitive applications and uses thereof
#152SYSTEM, METHOD, AND COMPUTER-PROGRAM PRODUCT FOR SCALABLE REGION-BASED REGISTER ALLOCATION IN COMPILERS
#153Use of name mangling techniques to encode cross procedure register assignment
#154Macroscalar processor architecture
#155REGISTER REDUCTION AND LIVENESS ANALYSIS TECHNIQUES FOR PROGRAM CODE
#156CREATING REGISTER DEPENDENCIES TO MODEL HAZARDOUS MEMORY DEPENDENCIES
#157Method for instruction pipelining on irregular register files
#158Method and apparatus for enregistering memory locations
#159Predication support in an out-of-order processor by selectively executing ambiguously renamed write operations
#160System and method of mapping shader variables into physical registers
#161Register allocation by puzzle solving
#162Technique for allocating register to variable for compiling
#163Compiling apparatus
#164Optimizing memory accesses for network applications using indexed register files
#165Pairing of spills for parallel registers
#166Macroscalar processor architecture
#167Replacing a variable in a use of the variable with a variant of the variable
#168INSTRUCTION SET ARCHITECTURE WITH OVERLAPPING FIELDS
#169Compiling method and storage medium therefor
#170Compiler register allocation and compilation
#171Systems and methods for efficiently using stack registers and storage medium therefor
#172Method for allocating registers for a processor
#173Instruction encoding to indicate whether to store argument registers as static registers and return address in subroutine stack
#174Compiling device, compiling method and recording medium
#175Profile-based global live-range splitting
#176Program code conversion
#177Program code conversion
#178Methods and apparatus for dynamic register scratching
#179System and Method for Efficiently Passing Information Between Compiler and Post-Compile-Time Software
#180Register allocation method and system for program compiling
#181Post-register allocation profile directed instruction scheduling
#182Systems, methods, and computer program products for packing instructions into register files
#183Method for allocating registers using simulated annealing controlled instruction scheduling
#184Use of different color sequences for variables of different sizes and different semantics
#185Tiered register allocation
#186Straight-line post-increment optimization for memory access instructions
#187Method and apparatus for register allocation in presence of hardware constraints
#188Apparatus and method for detecting base-register usage conflicts in computer code
#189Mechanism for ordering lists of local variables associated with a plurality of code blocks
#190Mechanism for flowing local variables across a plurality of code blocks
#191Processor arrangement and method for operation thereof
#192Macroscalar processor architecture
#193Bank assignment for partitioned register banks
#194Allocating automatic variables to different memory banks
#195Code verification method for limited resource microcircuits
#196Method and system for assigning register class through efficient dataflow analysis
#197Inter-procedural allocation of stacked registers for a processor
#198Data layout mechanism to reduce hardware resource conflicts
#199Method for register allocation during instruction scheduling
#200Method and system for allocating register locations in a memory during compilation
#201Methods and apparatuses for thread management of multi-threading
#202Restoring register values from stack memory using instruction with restore indication bit and de-allocation frame size stack pointer offset
#203Method and apparatus for program execution in a microprocessor
#204Methods and apparatuses for thread management of mult-threading
#205Device, system and method of allocating spill cells in binary instrumentation using one free register
#206Optimizing compiler
#207Register allocation and code spilling using interference graph coloring
#208Pairing of spills for parallel registers
#209Color selection schemes for storage allocation
#210Configuration of secondary processors
#211Adapting pre-compiled eBPF programs at runtime for the host kernel by offset inference
#212Color selection schemes for storage allocation
#213Balanced partitioning of neural network based on execution latencies
#214Compiler for optimizing memory allocations within cores
#215Dynamic taint tracking on mobile devices
#216Reconfiguration of address space based on loading short pointer mode application
#217Method of splitting register live ranges
#218Method of splitting register live ranges
#219Efficient error handling mechanisms in data storage systems
#220Conflict-free register allocation