INDIRECT PREFETCHER TRAINING

DYNAMIC RESOURCE PREDICTION USING LARGE CODE LANGUAGE MODELS

METHODS AND SYSTEMS FOR USING CACHED BUILDS IN SOFTWARE DEVELOPMENT

METHOD AND APPARATUS FOR COMPUTER OPERATION IMPROVEMENT BY FLATTENING MULTI-LEVEL DATA STRUCTURES TO OPTIMIZE POINTER CHASE

Compilation Optimization Method for Program Source Code and Related Product

Instruction prefetch mechanism

Shared compilation cache verification system

Shared compilation cache verification system

Prefetch kernels on data-parallel processors

Analysis for modeling data cache utilization

METHOD AND SYSTEM FOR PROVIDING A CONTEXT-SENSITIVE, NON-INTRUSIVE DATA PROCESSING OPTIMIZATION FRAMEWORK

CODE PREFETCH INSTRUCTION

Instruction prefetch mechanism

Firmware publication of multiple binary images

Systems and methods for data processing

Methods and systems for program optimization utilizing intelligent space exploration

Digitally coordinated dynamically adaptable clock and voltage supply apparatus and method

Information processing apparatus and information processing method

Systems and methods for data processing

Nested loops reversal enhancements

Thread prefetch mechanism

Prefetch kernels on data-parallel processors

Instruction prefetch mechanism

Fields hotness based object splitting

Cache efficient reading of result values in a column store database

Information processing apparatus, computer-readable recording medium storing therein compiler program, and compiling method

Compiler optimization for indirect array access operations

Cache efficient reading of result values in a column store database

Tuning of loop orders in blocked dense basic linear algebra subroutines

Method and device for distributing partitions on a multicore processor

INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND RECORDING MEDIUM RECORDING PROGRAM

Prefetch insensitive transactional memory

TECHNIQUE FOR INTER-PROCEDURAL MEMORY ADDRESS SPACE OPTIMIZATION IN GPU COMPUTING COMPILER

Prefetch insensitive transactional memory

Instruction prefetch mechanism

Circuitry with adaptive memory assistance capabilities

Post-compile cache blocking analyzer

Optimizing structures to fit into a complete cache line

Cache aware self-referential structure peeling

Prefetch insensitive transactional memory

Prefetch insensitive transactional memory

Compiling a parallel loop with a complex access pattern for writing an array for GPU and CPU

Compiling a parallel loop with a complex access pattern for writing an array for GPU and CPU

ACCELERATING SOFTWARE BUILDS

Automatic identification and generation of non-temporal store and load operations in a dynamic optimization environment

Arranging binary code based on call graph partitioning

Accelerating software builds

Accelerating software builds

Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads

Information processing device, storage medium, and method

Memory device having multiple read buffers for read latency reduction

Automatic recovery of application cache warmth

Arranging binary code based on call graph partitioning

Technologies for automatic reordering of sparse matrices

Prefetch insensitive transactional memory

Prefetch insensitive transactional memory

Prefetching with level of aggressiveness based on effectiveness by memory access type

Processor with efficient processing of recurring load instructions from nearby memory addresses

Arranging binary code based on call graph partitioning

Multiple window based segment prefetching

Set associative cache memory with heterogeneous replacement policy

Multiple data prefetchers that defer to one another based on prefetch effectiveness by memory access type

Information processing apparatus and compiling method

Automatic recovery of application cache warmth

Optimizing if statements in computer programming

Conditional branch instruction compaction for regional code size reduction

Optimizing if statements in computer programming

Computer-readable recording medium storing information processing program, information processing apparatus, and information processing method

Compiler caching for runtime routine redundancy tracking

Cache control device for prefetching using pattern analysis processor and prefetch instruction and prefetching method using cache control device

Conditional branch instruction compaction for regional code size reduction

Compile based obfuscation

Data splitting for recursive data structures

Compiling method and compiling device

Profiling binary code based on density

Conjugate code generation for efficient dynamic optimizations

Loop distribution detection program and loop distribution detection method

Implementing a jump instruction in a dynamic translator that uses instruction code translation and just-in-time compilation

Constraining prefetch requests to a processor socket

Method and node entity for enhancing content delivery network

Optimization of instructions to reduce memory access violations

Data splitting for multi-instantiated objects

Anticipated prefetching for a parent core in a multi-core chip

Computing apparatus, computing method, and computing program

Optimizing compiler performance by object collocation

Stack data management for software managed multi-core processors

Anticipated prefetching for a parent core in a multi-core chip

Heap data management for limited local memory(LLM) multi-core processors

Prefetch kernels on a graphics processing unit

Adaptive instruction prefetching and fetching memory system apparatus and method for microprocessor system

Method of prefetch optimizing by measuring execution time of instruction sequence cycling through each selectable hardware prefetch depth and cycling through disabling each software prefetch instruction

Autonomic hotspot profiling using paired performance sampling

Resource prefetching via sandboxed execution

Techniques to request stored data from a memory

Data processing apparatus and method for reducing storage requirements for temporary storage of data

Error detection within a memory

Monitoring accesses to memory in a multiprocessor system

Coordinated prefetching based on training in hierarchically cached processors

Methods and apparatuses for efficient load processing using buffers

Prefetch optimizer measuring execution time of instruction sequence cycling through each selectable hardware prefetch depth and cycling through disabling each software prefetch instruction of an instruction sequence of interest

Data prefetching and coalescing for partitioned global address space languages

Demand-driven algorithm to reduce sign-extension instructions included in loops of a 64-bit computer program

Algorithm for 64-bit address mode optimization

Technique for live analysis-based rematerialization to reduce register pressures and enhance parallelism

Algorithm for vectorization and memory coalescing during compiling

Program converting apparatus, program converting method, and medium

TECHNIQUE FOR INTER-PROCEDURAL MEMORY ADDRESS SPACE OPTIMIZATION IN GPU COMPUTING COMPILER

Methods and apparatus to access memory using runtime characteristics

Data prefetching method for distributed hash table DHT storage system, node, and system

Automatic caching of partial results while editing software

Method and node entity for enhancing content delivery network

Information processing device, terminal, server, and method for data transfer

Method and programming system for programming an automation component

AUTOMATION OF POST-LINKER FUNCTIONS IN EMBEDDED APPLICATIONS

Dynamically maintaining coherency within live ranges of direct buffers

Method and system for dynamic memory management

Prefetching irregular data references for software controlled caches

System and method for optimizing software transactional memory operations using static caching of memory objects

Rewriting branch instructions using branch stubs

Arranging binary code based on call graph partitioning

Dynamically rewriting branch instructions in response to cache line eviction

Variable-sized concurrent grouping for multiprocessing

Autonomic hotspot profiling using paired performance sampling

Structure layout optimizations

Multi-level buffer pool extensions

Arrangement method of programs to memory space, apparatus, and recording medium

Arranging binary code based on call graph partitioning

Rewriting branch instructions using branch stubs

Dynamically Rewriting Branch Instructions in Response to Cache Line Eviction

Shared prefetching to reduce execution skew in multi-threaded systems

Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads

Compiler assisted low power and high performance load handling based on load types

Efficient multi-level software cache using SIMD vector permute functionality

OPTIMIZATION OF AN APPLICATION PROGRAM

Methods and apparatuses for efficient load processing using buffers

Meta-data based data prefetching

Trace-assisted startup optimization from a virtual disk

PROGRAM OPTIMIZATION METHOD

Efficient parallel computation of dependency problems

Optimizing compiler performance by object collocation

Memory controller, memory system, semiconductor integrated circuit, and memory control method

Multiple pass compiler instrumentation infrastructure

Branch prediction path wrong guess instruction

Methods and apparatuses for compiler-creating helper threads for multi-threading

Method and system for data prefetching for loops based on linear induction expressions

Method and system generating execution file system device

Post-pass binary adaptation for software-based speculative precomputation

Apparatus, method and instruction for initiation of concurrent instruction streams in a multithreading microprocessor

Fine-grained software-directed data prefetching using integrated high-level and low-level code analysis optimizations

INDIRECT BRANCH PROCESSING PROGRAM AND INDIRECT BRANCH PROCESSING METHOD

Instruction cache

Optimized code generation targeting a high locality software cache

MINIMIZING MEMORY ACCESS CONFLICTS OF PROCESS COMMUNICATION CHANNELS

Efficient software cache accessing with handle reuse

Dynamically maintaining coherency within live ranges of direct buffers

Learning and cache management in software defined contexts

Event address register history buffers for supporting profile-guided and dynamic optimizations

Information processing system and information processing method

INFORMATION PROCESSING APPARATUS AND COMPILING METHOD

Prefetching irregular data references for software controlled caches

Data transfer optimized software cache for irregular memory references

Combining static and dynamic compilation to remove delinquent loads

Data transfer optimized software cache for regular memory references

Compiler capable of partitioning program and program partitioning method

Method and apparatus for partitioning programs to balance memory latency

Data splitting for recursive data structures

INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING SYSTEM

Tiling across loop nests with possible recomputation

Object relocation guided by data cache miss profile

Data layout using data type information

Apparatus and method for information processing enabling fast access to program

Compiler implemented software cache in which non-aliased explicitly fetched data are excluded

Uniform external and internal interfaces for delinquent memory operations to facilitate cache optimization

Profiling metrics for computer programs

Method and system for preloading page using control flow

Method and apparatus for merging critical sections

System, method, and computer program product for conditionally suspending issuing instructions of a thread

Software solution for cooperative memory-side and processor-side data prefetching

System and method for recompiling code based on locality domain and thread affinity in NUMA computer systems

Method and system for dynamic memory management

Program control device and program control method

COMPILER ASSISTED RE-CONFIGURABLE SOFTWARE IMPLEMENTED CACHE

Compiling device, list vector area assignment optimization method, and computer-readable recording medium having compiler program recorded thereon

Method and system for generating prefetch information for multi-block indirect memory access chains

Compiler implemented software cache method in which non-aliased explicitly fetched data are excluded

Compiling source code

Method and system for optimizing performance based on cache analysis

Learning and cache management in software defined contexts

Automatic caching generation in network applications

Synchronized storage providing multiple synchronization semantics

Blocking of nested loops having feedback or feedforward indexes

Automatic identification of application-specific functional units with architecturally visible storage

METHODS AND APPARATUS TO OPTIMIZE PROCESSING THROUGHPUT OF DATA STRUCTURES IN PROGRAMS

Method and apparatus for software-assisted data cache and prefetch control

Optimizing cache efficiency within application software

Facilitating communication and synchronization between main and scout threads

Method and apparatus for software scouting regions of a program

Program translation method and program translation apparatus

System and method for determining the cacheability of code at the time of compiling

Automatic generation of software-controlled caching and ordered synchronization

Preemptive multitasking employing software emulation of directed exceptions in a multithreading processor

Software managed cache optimization system and method for multi-processing systems

Dynamic prefetching of hot data streams

Fine-grained software-directed data prefetching using integrated high-level and low-level code analysis optimizations

Method and apparatus for improving data cache performance using inter-procedural strength reduction of global objects

Cost-aware design-time/run-time memory management methods and apparatus

Data prefetch method for indirect references

Program conversion apparatus and processor

Synchronized storage providing multiple synchronization semantics

Compiler with cache utilization optimizations

Apparatus, method, and instruction for software management of multiple computational contexts in a multithreaded microprocessor

Grouping frequently referenced data items to co-locate for cache utilization

Cache coloring based on dynamic function flow

Data layout mechanism to reduce hardware resource conflicts

Data processing apparatus and compiler apparatus

Method and system for code modification based on cache structure

Integrated mechanism for suspension and deallocation of computational threads of execution in a processor

Mechanisms for dynamic configuration of virtual processor resources

Apparatus, method, and instruction for initiation of concurrent instruction streams in a multithreading microprocessor

Method for prefetching recursive data structure traversals

Ordering of high use program code segments using simulated annealing

Compiler apparatus for optimizing high-level language programs using directives

Methods and apparatus for reducing memory latency in a software application

Compiler apparatus and linker apparatus

Computer system, compiler apparatus, and operating system

Methods and apparatuses for compiler-creating helper threads for multi-threading

Method and apparatus for hardware data speculation to support memory optimizations

Methods and apparatus to pre-execute instructions on a single thread

Integrated mechanism for suspension and deallocation of computational threads of execution in a processor

Automatically reordering variables as a part of compiling and linking source code

Systems and methods for array structure processing

Efficient code cache management in presence of infrequently used complied code fragments

Cache contention management on a multicore processor based on the degree of contention exceeding a threshold