Parallel Execution of Cells in Directed Acyclic Graph-Driven Notebook Environment

TECHNIQUES FOR PARALLEL EXECUTION

ACCELERATOR INCLUDING HIERARCHICAL MEMORY

Systems and methods to manage sub-chart dependencies with directed acyclic graphs

Concept for Evaluating Hardware Tracing Records

AUTOMATIC TUNING OF A HETEROGENEOUS COMPUTING SYSTEM

Partitioning and parallel loading of property graphs with constraints

Compiler device, instruction generation method, program, compiling method, and compiler program

COMPUTER-READABLE RECORDING MEDIUM STORING PROGRAM AND INFORMATION PROCESSING METHOD

Locate neural network performance hot spots

Techniques for parallel execution

Memory-bound scheduling

Allocating variables to computer memory

Secure IDS certificate verification for a primary platform

Offloading server and offloading program

Pre-instruction scheduling rematerialization for register pressure reduction

Information processing method and computer-readable recording medium having stored therein optimization program

Large lookup tables for an image processor

ADAPTIVE COMPILATION OF QUANTUM COMPUTING JOBS

Application interface on multiple processors

Annotations for parallelization of user-defined functions with flexible partitioning

Compiler for translating between a virtual image processor instruction set architecture (ISA) and target hardware having a two-dimensional shift array structure

Compiling and combining instructions from different branches for execution in a processing element of a multithreaded processor

TECHNIQUES FOR TRANSFORMING SERIAL PROGRAM CODE INTO KERNELS FOR EXECUTION ON A PARALLEL PROCESSOR

Method and apparatus for detecting inter-instruction data dependency

TECHNIQUE FOR INTER-PROCEDURAL MEMORY ADDRESS SPACE OPTIMIZATION IN GPU COMPUTING COMPILER

Technologies for indirectly calling vector functions

Circuitry with adaptive memory assistance capabilities

Compiler for translating between a virtual image processor instruction set architecture (ISA) and target hardware having a two-dimensional shift array structure

Systems and methods for automatic computer code parallelization

Program code optimization for reducing branch mispredictions

Method and device for processing an irregular application

Vector processing system

Method and apparatus to create register windows for parallel iterations to achieve high performance in HW-SW codesigned loop accelerator

Systems and methods for generating code for parallel processing units

Software optimization for multicore systems

Preprocessing tensor operations for optimal compilation

Supporting binary translation alias detection in an out-of-order processor

Compiler architecture for programmable application specific integrated circuit based network devices

Automatically enabling a read-only cache in a language in which two arrays in two different variables may alias each other

General purpose distributed data parallel computing using a high level language

Application interface on multiple processors

Unaligned instruction relocation

Compiler for translating between a virtual image processor instruction set architecture (ISA) and target hardware having a two-dimensional shift array structure

VLIW type instruction packet structure and processor suitable for processing such an instruction packet

Advanced interactive command-line front-end for graph analysis systems

Incremental interprocedural dataflow analysis during compilation

Reuse of decoded instructions

Compiler for translating between a virtual image processor instruction set architecture (ISA) and target hardware having a two-dimensional shift array structure

Unaligned instruction relocation

Unaligned instruction relocation

Compiler method, parallel processing method, and compiler apparatus

Application interface on multiple processors

Utilizing special purpose elements to implement a FSM

Algorithm to achieve optimal layout of decision logic elements for programmable network devices

Algorithm to achieve optimal layout of instruction tables for programmable network devices

Algorithm to derive logic expression to select execution blocks for programmable network devices

Code processor to build orthogonal execution blocks for programmable network devices

Compiler architecture for programmable application specific integrated circuit based network devices

Code generator for programmable network devices

Hybrid parallelization strategies for machine learning programs on top of mapreduce

Loop nest parallelization without loop linearization

System, method, and computer program product for implementing large integer operations on a graphics processing unit

Combining instructions from different branches for execution in a single n-way VLIW processing element of a multithreaded processor

Method and system for generating object code to facilitate predictive memory retrieval

System for an instruction set agnostic runtime architecture

Compile based obfuscation

Extending superword level parallelism

Extending superword level parallelism

System and methods for collaborative query processing for large scale data processing with software defined networking

Compiler method and compiler apparatus for optimizing a code by transforming a code to another code including a parallel processing instruction

Interleaving data accesses issued in response to vector access instructions

Control flow optimization for efficient program code execution on a processor

Instruction definition to implement load store reordering and optimization

Method and system for automated process distribution

System and method for energy aware program development

Auto multi-threading in macroscalar compilers

Increasing macroscalar instruction level parallelism

Method and apparatus for exploiting data locality in dynamic task scheduling

System, method, and computer program product for implementing large integer operations on a graphics processing unit

Solution to divergent branches in a SIMD core using hardware pointers

Application interface on multiple processors

Code conversion method, program, and system for garbage collection

Enhanced instruction scheduling during compilation of high level source code for improved executable code

Parallel processing in human-machine interface applications

Method and system for generating object code to facilitate predictive memory retrieval

Code generation method and information processing apparatus

Instruction scheduling for reducing register usage based on dependence depth and presence of sequencing edge in data dependence graph

Optimizing texture commands for graphics processing unit

Applicaton interface on multiple processors

Demand-driven algorithm to reduce sign-extension instructions included in loops of a 64-bit computer program

Algorithm for 64-bit address mode optimization

Technique for live analysis-based rematerialization to reduce register pressures and enhance parallelism

Algorithm for vectorization and memory coalescing during compiling

TECHNIQUE FOR INTER-PROCEDURAL MEMORY ADDRESS SPACE OPTIMIZATION IN GPU COMPUTING COMPILER

Interleaving data accesses issued in response to vector access instructions

Systems and methods for parallel execution of a portion of a script by interpreting comments in the script as parallel control statements

Modular ASL component

Method and system for dynamic memory management

Pipelined loop parallelization with pre-computations

Runtime dependence-aware scheduling using assist thread

Utilizing special purpose elements to implement a FSM

Data processing circuit with a plurality of instruction modes for processing time-stationary encoded instructions, and method of operating/scheduling such data circuit

Systems and methods for compiler-based full-function vectorization

Asynchronous workflows

Program converting apparatus and program conversion method

Compiling device and compiling method

Method and system for generating object code to facilitate predictive memory retrieval

Using vector atomic memory operation to handle data of different lengths

Runtime dependence-aware scheduling using assist thread

General purpose distributed data parallel computing using a high level language

Fast vector masking algorithm for conditional data selection in SIMD architectures

Data processing circuit with a plurality of instruction modes, method of operating such a data circuit and scheduling method for such a data circuit

Energy/performance with optimal communication in dynamic parallelization of single threaded programs

System and method for processor with predictive memory retrieval assist

Modular ASL component

ARITHMETIC DEVICE, ARITHMETIC METHOD, HARD DISC CONTROLLER, HARD DISC DEVICE, PROGRAM CONVERTER, AND COMPILER

Digital data processing method and system

Generation of a progress notification in a software loop

System and method for instruction latency reduction in graphics processing

Method and apparatus for interactive scheduling of VLIW assembly code

STRAND-BASED COMPUTING HARDWARE AND DYNAMICALLY OPTIMIZING STRANDWARE FOR A HIGH PERFORMANCE MICROPROCESSOR SYSTEM

Method and apparatus for automatic second-order predictive commoning

System and method for processor with predictive memory retrieval assist

Systems, methods and computer products for cross-thread scheduling

Method and apparatus for ordering code based on critical sections

Scheduling multithreaded programming instructions based on dependency graph

OPTIMISED COMPILATION METHOD DURING CONDITIONAL BRANCHING

Method and Apparatus For Generating Execution Equivalence Information

Application interface on multiple processors

Method and system for reducing memory reference overhead associated with treadprivate variables in parallel programs

Configuring a dependency graph for dynamic by-pass instruction scheduling

Reordering application code to improve processing performance

Method, apparatus and computer program for executing a program

Code generation for complex arithmetic reduction for architectures lacking cross data-path support

Optimization of a target program

Method and system for automated process distribution

METHODS AND APPARATUS TO OPTIMIZE COMPUTER INSTRUCTIONS

Method and apparatus for generating data parallel select operations in a pervasively data parallel system

Pervasively data parallel information handling system and methodology for generating data parallel select operations

Method and system for dynamic memory management

Framework for integrated intra- and inter-loop aggregation of contiguous memory accesses for SIMD vectorization

System and method for simulating hardware interrupts

Optimizing code motion with delayed exception handling

Method and apparatus for moving area operator definition instruction statements within control flow structures

Method, system and program product for detecting and managing unwanted synchronization

Drive and method for simulating the insertion of a new record

Methods and apparatus for multi-core processing with dedicated thread management

Post-register allocation profile directed instruction scheduling

Compilation for a SIMD RISC processor

Dynamic instruction sequence selection during scheduling

Code outlining without trampolines

Method and system for reducing memory reference overhead associated with threadprivate variables in parallel programs

Alignment of variable length program instructions within a data processing apparatus

Compiler apparatus

Systems and methods for re-ordering instructions

Technique for processing a computer program

Method and system for optimizing operations on memory device

Trace based signal scheduling and compensation code generation

Pipelined instruction processor with data bypassing and disabling circuit

Methods and systems for ordering instructions using future values

System and method for simulating hardware interrupts

Method and system for generating object code to facilitate predictive memory retrieval

Method and apparatus for automatic second-order predictive commoning

Method and system for configuring a dependency graph for dynamic by-pass instruction scheduling

System and method for processor with predictive memory retrieval assist

Computer system for data processing and method for the transfer of an array segment of an affine-indexed multi-dimensional array referenced in a loop nest from a first memory to a second memory

Systems and methods for replacing NOP instructions in a first program with instructions of a second program

Scheduling of instructions in program compilation

Framework for integrated intra- and inter-loop aggregation of contiguous memory accesses for SIMD vectorization

Signal processing apparatus and method thereof

Method and apparatus for generating code for scheduling the execution of binary code

Instruction scheduling

Resource-aware scheduling for compilers

Tail duplicating during block layout

Information processing system and code generation method

Method for register allocation during instruction scheduling

Method, apparatus and computer program for executing a program by incorporating threads

Method for minimizing spill in code scheduled by a list scheduler

Microprocessor using genetic algorithm

Fast interference graph construction for a binary tree of interval nodes

Quantum instruction compiler for optimizing hybrid algorithms

Language agnostic pipeline packager for machine learning

Applications for hardware accelerators in computing systems

Applications for hardware accelerators in computing systems

Quantum instruction compiler for optimizing hybrid algorithms

Pipelined data cryptography device and method

Programming in a multiprocessor environment