189636 ⎘
Arrangements for software engineering; Transformation of program code; Compilation; Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions Data distribution
Sub-classes:BUFFER-PIPELINE MANAGER (BPM) FOR RECONFIGURABLE PROCESSORS
#2DEVICES FOR FACILITATING STREAMING IN A LOCAL NETWORK WITH A CLIENT-SERVER ARCHITECTURE
#3SYSTEMS AND METHODS FOR FACILITATING STREAMING IN A LOCAL NETWORK WITH MULTIPLE SUBNETS
#4COMPILER-BASED SYNCHRONIZATION FOR DATAFLOW GRAPHS ON COARSE-GRAINED RECONFIGURABLE ARCHITECTURES
#5UPDATING MEDIA DEVICES IN A LOCAL NETWORK WITH A CLIENT-SERVER ARCHITECTURE
#6CREDIT-BASED ARBITRATION FOR A RECONFIGURABLE DATA PROCESSOR
#7ADAPTIVE SEARCH-BASED ALLOCATION OF COMPUTATIONS TO SYNCHRONIZED, INTERCONNECTED PROCESSING ELEMENTS FOR IMPLEMENTING MACHINE LEARNING NETWORKS
#8FACILITATING STREAMING IN A LOCAL NETWORK WITH A CLIENT-SERVER ARCHITECTURE
#9DATA COMMUNICATION WITH REMOTE OPERATION OF A VEHICLE
#10SYSTEM FOR AUTO-PARALLELIZATION OF PROCESSING CODES FOR MULTI-PROCESSOR SYSTEMS WITH OPTIMIZED LATENCY, AND METHOD THEREOF
#11FUSION FOR MULTI-LAYERED COMPUTATIONAL GRAPHS
#12VOICE COMMAND INTEGRATION FOR LOCAL NETWORK CONNECTED DEVICES
#13METHOD AND APPARATUS FOR USING A PACKET ARCHITECTURE TO PROCESS NEURAL NETWORKS IN A NEURAL PROCESSING UNIT
#14SYSTEMS AND METHODS FOR FACILITATING STREAMING IN A LOCAL NETWORK WITH MULTIPLE SUBNETS
#15COMPILING TENSOR OPERATORS FOR NEURAL NETWORK MODELS BASED ON TENSOR TILE CONFIGURATIONS
#16SMART TV OPERATING SYSTEM ARRANGEMENTS FOR LOCAL NETWORK CONNECTED TELEVISION RECEIVERS
#17Sparsity uniformity enforcement for multicore processor
#18Programming a coarse grained reconfigurable array through description of data flow graphs
#19REMOTE APPLICATION MODERNIZATION
#20Head of line blocking mitigation in a reconfigurable data processor
#21Electronic device and controlling method of electronic device
#22System and Method for User Interactive Pipelining of a Computing Application
#23COMPILER-BASED INPUT SYNCHRONIZATION FOR PROCESSOR WITH VARIANT STAGE LATENCIES
#24Voice command integration for local network connected devices
#25Sparsity uniformity enforcement for multicore processor
#26METHOD OF DISTRIBUTED GRAPH LOADING FOR MINIMAL COMMUNICATION AND GOOD BALANCE VIA LAZY MATERIALIZATION AND DIRECTORY INDIRECTION USING INDEXED TABULAR REPRESENTATION
#27Updating media devices in a local network with a client-server architecture
#28Systems and methods for facilitating streaming in a local network with multiple subnets
#29System and method for generating a video signal
#30Engine to propagate data across systems
#31DEVICES FOR FACILITATING STREAMING IN A LOCAL NETWORK WITH A CLIENT-SERVER ARCHITECTURE
#32Facilitating streaming in a local network with a client-server architecture
#33Accelerating application modernization
#34Engine to propagate data across systems
#35Hardware acceleration method, compiler, and device
#36Systems and methods for minimizing communications
#37Cognitive automation-based engine to propagate data across systems
#38Vehicle master device, rewrite target group administration method, computer program product and data structure of specification data
#39Remote application modernization
#40Accelerating application modernization
#41PROCESS FOR CONSTRUCTING A SIGNATURE CHARACTERISTIC OF THE ACCESSES, BY A MICROPROCESSOR, OF A MEMORY
#42Rescheduling JIT compilation based on jobs of parallel distributed computing framework
#43Method of distributed graph loading for minimal communication and good balance via lazy materialization and directory indirection using indexed tabular representation
#44Thread associated memory allocation and memory architecture aware allocation
#45Shared local memory tiling mechanism
#46Systems and methods for energy proportional scheduling
#47Systems and methods for minimizing communications
#48Hardware acceleration method, compiler, and device
#49Shared local memory tiling mechanism
#50Optimize control-flow convergence on SIMD engine using divergence depth
#51Method of distributed graph loading for minimal communication and good balance via lazy materialization and directory indirection using indexed tabular representation
#52Methods and apparatus to convert a non-series-parallel control flow graph to data flow
#53Computer system and method for parallel program code optimization and deployment
#54Incremental parallel processing of data
#55Shared local memory tiling mechanism
#56Compiling a parallel loop with a complex access pattern for writing an array for GPU and CPU
#57Compiling a parallel loop with a complex access pattern for writing an array for GPU and CPU
#58Optimize control-flow convergence on SIMD engine using divergence depth
#59Thread associated memory allocation and memory architecture aware allocation
#60Hardware acceleration method, compiler, and device
#61Software service execution apparatus, system, and method
#62Iterative evaluation of data through SIMD processor registers
#63AUTO-VECTORIZATION IN JUST-IN-TIME COMPILERS FOR DYNAMICALLY TYPED PROGRAMMING LANGUAGES
#64Global data flow optimization for machine learning programs
#65Apparatus and method for handling registers in pipeline processing
#66Auto-vectorization in just-in-time compilers for dynamically typed programming languages
#67Compiler method, parallel processing method, and compiler apparatus
#68Systems and methods for efficient determination of task dependences after loop tiling
#69Systems and methods for energy proportional scheduling
#70Systems and methods for minimizing communications
#71Technologies for low-level composable high performance computing libraries
#72Information processing apparatus, communication method and information processing system for communication of global data shared by information processing apparatuses
#73Incremental parallel processing of data
#74Optimize control-flow convergence on SIMD engine using divergence depth
#75Method and apparatus for compiling code based on a dependency tree
#76Data processing service
#77Hierarchical resource pools in a linker
#78Analyzing update conditions for shared variable directory information in a parallel computer
#79Analyzing update conditions for shared variable directory information in a parallel computer
#80Compiler-controlled region scheduling for SIMD execution of threads
#81Data-parallel computation management
#82Vectorization of shaders
#83Optimizing data partitioning for data-parallel computing
#84Arithmetic and control unit, arithmethic and control method, program and parallel processor
#85CO-RANGE PARTITION FOR QUERY PLAN OPTIMIZATION AND DATA-PARALLEL PROGRAMMING MODEL
#86Tile communication operator
#87Parallel programming interface to dynamicaly allocate program portions
#88Indexable type transformations
#89Generating an encoded package profile
#90Generating an encoded package profile based on executing host processes
#91System, methods and apparatus for program optimization for multi-threaded processor architectures
#92Memory management method, information processing device, program creation method, and program
#93MULTIPLE TASK MANAGEMENT BETWEEN PROCESSORS
#94Communication scheduling within a parallel processing system
#95Tracing command execution in a parallel processing system
#96SOFTWARE DEVELOPMENT FOR PARALLEL PROCESSING SYSTEMS
#97Method and system for reducing memory reference overhead associated with treadprivate variables in parallel programs
#98Parallel programming interface to dynamically allocate program portions
#99Efficient data loading in a data-parallel processor
#100Method for mapping applications on a multiprocessor platform/system
#101Method and system for reducing memory reference overhead associated with threadprivate variables in parallel programs
#102Splitting the computation space to optimize parallel code
#103Method and system for memory management within machine learning inference engine
#104Method and system to update weight and bias in partitioned on-chip memory in an inference engine with multiple processing tiles
#105Method and system to expand accessible on-chip memory (OCM) of an inference engine
#106Method and apparatus for performing machine learning operations in parallel on machine learning hardware
#107Method and apparatus for performing machine learning operations in parallel on machine learning hardware
#108Methods and apparatus for automatic communication optimizations in a compiler based on a polyhedral representation
#109Methods and apparatus for automatic communication optimizations in a compiler based on a polyhedral representation
#110Stream adapter for batch-oriented processing frameworks
#111Distributed model compilation