189703 ⎘
Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs; Arrangements for executing machine instructions, e.g. instruction decode; Arrangements for executing specific machine instructions to perform operations for flow control Instruction skipping instructions, e.g. SKIP
SKIPPING PREDICTIONS ON A FLUSH
#2APPARATUS AND SYSTEM FOR PROCESSING FUSION OF HETEROGENEOUS DATA INCLUDING SYNCHRONIZED INFRARED IMAGES
#3PATCH EXECUTION METHOD AND APPARATUS
#4PREDICTION CIRCUITRY
#5CONTROL REGISTER FOR STORING INSTRUCTION SIZE INFORMATION
#6HASHING FOR DEDUPLICATION THROUGH SKIPPING SELECTED DATA
#7METHODS AND SYSTEM FOR IMPROVED PROCESSING OF SEQUENTIAL DATA IN A NEURAL NETWORK
#8APPARATUS, NPU AND CHIPSET IMPLEMENTED FOR FUSION NEURAL NETWORK
#9Scatter and Gather Streaming Data through a Circular FIFO
#10METHOD AND APPARATUS FOR DETERMINING BINARY FUNCTION ENTRY
#11Branch prediction method, branch prediction apparatus, processor, medium, and device
#12NPU implemented for fusion-artificial neural network to process heterogeneous data provided by heterogeneous sensors
#13METHOD TO OPTIMIZE STORAGE PARTITION REDISCOVERY
#14Method performed by a microcontroller for managing a NOP instruction and corresponding microcontroller
#15Sparse systolic array design
#16Systems and methods to skip inconsequential matrix operations
#17Dependency skipping in a load-compare-jump sequence of instructions by incorporating compare functionality into the jump instruction and auto-finishing the compare instruction
#18BITWISE PRODUCT-SUM ACCUMULATIONS WITH SKIP LOGIC
#19NPU implemented for artificial neural networks to process fusion of heterogeneous data received from heterogeneous sensors
#20Managing execution of continuous delivery pipelines for a cloud platform based data center
#21Handling of single-copy-atomic load/store instruction with a memory access request shared by micro-operations
#22Non-transitory computer-readable recording medium, compilation method, and compiler device
#23NPU implemented for artificial neural networks to process fusion of heterogeneous data received from heterogeneous sensors
#24METHOD AND APPARATUS OF OPERATING A NEURAL NETWORK
#25Method performed by a microcontroller for managing a NOP instruction and corresponding microcontroller
#26Hashing for deduplication through skipping selected data
#27RISC-V BRANCH PREDICTION METHOD, DEVICE, ELECTRONIC DEVICE AND STORAGE MEDIUM
#28Reverse engineering detection by counting consecutive incremental branch instructions in an instruction register of a processor
#29Scatter and gather streaming data through a circular FIFO
#30Microprocessor with high-efficiency decoding of complex instructions
#31Systems and methods to skip inconsequential matrix operations
#32Structured weight based sparsity in an artificial neural network
#33Skip-over offset branch prediction
#34Optimized trampoline design for fast software tracing
#35MICRO-OP FUSION FOR NON-ADJACENT INSTRUCTIONS
#36Indirect instruction predication
#37Indirect instruction predication
#38Picoengine having a hash generator with remainder input S-box nonlinearizing
#39Efficient conditional instruction having companion load predicate bits instruction
#40Skip instruction to skip a number of instructions on a predicate
#41Processor that leapfrogs MOV instructions
#42Control flow in a thread-based environment without branching
#43BRANCH MISPREDICTION BEHAVIOR SUPPRESSION USING A BRANCH OPTIONAL INSTRUCTION
#44Controlling the execution of adjacent instructions that are dependent upon a same data condition
#45Applying non-homogeneous properties to multiple video processing units (VPUs)
#46Computer processor and method with short forward jump instruction inhibiting
#47Data processing apparatus and method for handling vector instructions
#48Multi-chip rendering with state control
#49System and method for generating and using predicates within a single instruction packet
#50Microcontroller comprising a plurality of registers and instruction modes
#51Method and system having instructions with different execution times in different modes, including a selected execution time different from default execution times in a first mode and a random execution time in a second mode
#52Processor cluster implementing conditional instruction skip
#53Applying non-homogeneous properties to multiple video processing units (VPUs)
#54Data processing system using independent memory and register operand size specifiers and method thereof
#55Control register for storing instruction size information
#56Systolic multiply delayed accumulate processor architecture
#57Down-sampling of negative signals used in training machine-learned model