189719 ⎘
Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs; Arrangements for executing machine instructions, e.g. instruction decode; Register arrangements; Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers Register windows
Permute Instructions for Register-Based Lookups
#2Diffractive optical element with undiffracted light expansion for eye safe operation
#3Efficient inter-thread communication between hardware processing threads of a hardware multithreaded processor by selective aliasing of register blocks
#4Optimize bound information accesses in buffer protection
#5Data loading
#6DATA PROCESSING METHOD AND DEVICE
#7Information processing apparatus and semiconductor device
#8Compliance aware service registry and load balancing
#9Synchronizing multiple processing systems
#10Asynchronous flush and restore of distributed history buffer
#11Dynamic fusion based on operand size
#12Compliance aware service registry and load balancing
#13Intensity-modulated light pattern for active stereo
#14Method and apparatus to create register windows for parallel iterations to achieve high performance in HW-SW codesigned loop accelerator
#15Super-resolving depth map by moving pattern projector
#16Communication between threads of multi-thread processor
#17Tightly coupled processor arrays using coarse grained reconfigurable architecture with iteration level commits
#18Device and processing architecture for resolving execution pipeline dependencies without requiring no operation instructions in the instruction memory
#19Register spill management for general purpose registers (GPRs)
#20History buffer with single snoop tag for multiple-field registers
#21Processor efficiency by combining working and architectural register files
#22Processor efficiency by combining working and architectural register files
#23Allocation of alias registers in a pipelined schedule
#24Register window performance via lazy register fills
#25Parallel memories for multidimensional data access
#26Diffractive optical element with undiffracted light expansion for eye safe operation
#27Extracting true color from a color and infrared sensor
#28Depth imaging system based on stereo vision and infrared radiation
#29Super-resolving depth map by moving pattern projector
#30Active stereo with adaptive support weights from a separate image
#31Apparatus and method for sliding window data access
#32Apparatus and computer program product for handling network packets using a pipeline of elements
#33Tracking operand liveness information in a computer system and performing function based on the liveness information
#34Scalable decode-time instruction sequence optimization of dependent instructions
#35Modified balanced throughput data-path architecture for special correlation applications
#36Apparatus for processing register window overflow and underflow
#37Reducing power consumption and resource utilization during miss lookahead
#38Prefetching load data in lookahead mode and invalidating architectural registers instead of writing results for retiring instructions
#39Tracking operand liveness information in a computer system and performing function based on the liveness information
#40Scalable decode-time instruction sequence optimization of dependent instructions
#41Processor and method providing instruction support for instructions that utilize multiple register windows
#42Instruction support for performing montgomery multiplication
#43Computer system and method of adapting a computer system to support a register window architecture
#44Register file having multiple windows and a current window pointer
#45Accessing a multibank register file using a thread identifier
#46Multithread processor and method of controlling multithread processor
#47System for protecting supervisor mode data from user code
#48Information processing apparatus and control method
#49Instruction execution control device and instruction execution control method
#50Instruction processing apparatus
#51Information processing apparatus and method of controlling register
#52CHECKPOINTING IN A PROCESSOR THAT SUPPORTS SIMULTANEOUS SPECULATIVE THREADING
#53Register set used in multithreaded parallel processor architecture
#54Method and system for register management
#55ARITHMETIC PROCESSING UNIT
#56Computer system and method of adapting a computer system to support a register window architecture
#57Using windowed register file to checkpoint register state
#58System for protecting sensitive data from user code in register window architecture
#59Multiple-thread processor with in-pipeline, thread selectable storage
#60Tightly coupled scalar and boolean processor with result vector subunit controlled by instruction flow
#61Register window system and method that stores the next register window in a temporary buffer
#62VIRTUAL REGISTER SET EXPANDING PROCESSOR INTERNAL STORAGE
#63Processor transferring multiple working register windows transfers global registers only for select exception handling
#64Multithread processor and register control method
#65Apparatus and method for separate asymmetric control processing and data path processing in a dual path processor
#66Microprocessor that carries out context switching by shifting context information stored in a ringed shift register
#67Method and apparatus for register stack implementation using micro-operations
#68Method and apparatus for alleviating register window size constraints
#69Save and restore register
#70Hardware for supporting OS driven load anticipation based on variable sized load units