189729 ⎘
Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs; Arrangements for executing machine instructions, e.g. instruction decode; Instruction analysis, e.g. decoding, instruction word fields; Decoding the operand specifier, e.g. specifier format with implied specifier, e.g. top of stack
ENCODING AND DECODING VARIABLE LENGTH INSTRUCTIONS
#2Implicit Global Pointer Relative Addressing for Global Memory Access
#3SCALAR CORE INTEGRATION
#4Scalar core integration
#5Graph Instruction Processing Method and Apparatus
#6COALESCING ADJACENT GATHER/SCATTER OPERATIONS
#7Scalar core integration
#8Encoding and decoding variable length instructions
#9Coalescing adjacent gather/scatter operations
#10Scalar core integration
#11Scalar core integration
#12Call stack sampling
#13Systems and methods for controlling machine operations using stack entries comprising instruction configuration parameters
#14Encoding and decoding variable length instructions
#15Arithmetic processing apparatus and method for selecting an executable instruction based on priority information written in response to priority flag comparison
#16Computer processor employing operand data with associated meta-data
#17Automatic predication of hard-to-predict convergent branches
#18Processors, methods, systems, and instructions to generate sequences of integers in which integers in consecutive positions differ by a constant integer stride and where a smallest integer is offset from zero by an integer offset
#19Coalescing adjacent gather/scatter operations
#20Real time stack protection
#21EMPLOYING A STACK ACCELERATOR FOR STACK-TYPE ACCESSES
#22Apparatus and method for complex multiply and accumulate
#23Apparatus and method for performing operations on capability metadata
#24Implicit global pointer relative addressing for global memory access
#25Providing efficient recursion handling using compressed return address stacks (CRASs) in processor-based systems
#26Unified logic for aliased processor instructions
#27Tensor processor instruction set architecture
#28Tensor register files
#29Multiple register memory access instructions, processors, methods, and systems
#30Multiple register memory access instructions, processors, methods, and systems
#31Multiple register memory access instructions, processors, methods, and systems
#32Multiple register memory access instructions, processors, methods, and systems
#33Multiple register memory access instructions, processors, methods, and systems
#34Processors, methods, systems, and instructions to generate sequences of integers in which integers in consecutive positions differ by a constant integer stride and where a smallest integer is offset from zero by an integer offset
#35Processors, methods, systems, and instructions to generate sequences of integers in which integers in consecutive positions differ by a constant integer stride and where a smallest integer is offset from zero by an integer offset
#36Processors, methods, systems, and instruction conversion modules for instructions with compact instruction encodings due to use of context of a prior instruction
#37Multiple register memory access instructions, processors, methods, and systems
#38Architectural register replacement for instructions that use multiple architectural registers
#39Fetch unit for predicting target for subroutine return instructions
#40Multiple register memory access instructions, processors, methods, and systems
#41Indirect instruction predication
#42Indirect instruction predication
#43Method and apparatus for SIMD structured branching
#44Vector register addressing and functions based on a scalar register data value
#45Packed data rearrangement control indexes generation processors, methods, systems and instructions
#46Processors, methods, systems, and instructions to generate sequences of integers in which integers in consecutive positions differ by a constant integer stride and where a smallest integer is offset from zero by an integer offset
#47Processors, methods, systems, and instructions to generate sequences of consecutive integers in numerical order
#48Methods and apparatus for creating and executing a packet of instructions organized according to data dependencies between adjacent instructions and utilizing networks based on adjacencies to transport data in response to execution of the instructions
#49Load pair disjoint facility and instruction therefor
#50PROCESSOR FOR EXECUTING HIGHLY EFFICIENT VLIW
#51Vector instruction execution to load vector data in registers of plural vector units using offset addressing logic
#52Prioritized assignment of sub-range registers of circularly addressable extended register file to loop variables in RISC processor
#53Operating a stack of information in an information handling system
#54Load pair disjoint facility and instruction therefore
#55Processor, co-processor, information processing system, and method for controlling processor, co-processor, and information processing system
#56Interconnection network connecting operation-configurable nodes according to one or more levels of adjacency in multiple dimensions of communication in a multi-processor and a neural processor
#57Interconnection networks and methods of construction thereof for efficiently sharing memory and processing in a multiprocessor wherein connections are made according to adjacency of nodes in a dimension
#58METHOD OF ENCODING USING INSTRUCTION FIELD OVERLOADING
#59Transfer triggered microcontroller with orthogonal instruction set
#60MICROCOMPUTER AND DIVIDING CIRCUIT
#61Processor for executing highly efficient VLIW
#62Compare, swap and store facility with no external serialization
#63Method and arrangements for multipath instruction processing
#64Interconnection network and method of construction thereof for efficiently sharing memory and processing in a multi-processor wherein connections are made according to adjacency of nodes in a dimension
#65RAW Hazard Detection and Resolution for Implicitly Used Registers
#66Processor for executing highly efficient VLIW
#67Load Relative and Store Relative Facility and Instructions Therefore
#68Thread optimized multiprocessor architecture
#69MICROCOMPUTER AND DIVIDING CIRCUIT
#70X87 fused multiply-add instruction
#71System and method for translating non-native instructions to native instructions for processing on a host processor
#72Compare, swap and store facility with no external serialization
#73Processor and processing method for reusing arbitrary sections of program code
#74Handling of conditional instructions in a data processing apparatus
#75Data processor
#76Dynamic retention of hardware register content in a computer system
#77Rounding correction for add-shift-round instruction with dual-use source operand for DSP
#78Add-shift-round instruction with dual-use source operand for DSP
#79Instruction with dual-use source providing both an operand value and a control value
#80Processor composed of memory nodes that execute memory access instructions and cooperate with execution nodes to execute function instructions
#81Programmable and scalable microcontroller architecture
#82Method for executing structured symbolic machine code on a microprocessor
#83Register read circuit using the remainders of modulo of a register number by the number of register sub-banks
#84System and method for translating non-native instructions to native instructions for processing on a host processor
#85Microcomputer and dividing circuit
#86Chip multiprocessor for media applications
#87MAXQ microcontroller
#88Register addressing