189752 ⎘
Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs; Arrangements for executing machine instructions, e.g. instruction decode; Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes; Indexed addressing, i.e. using more than one address operand using wraparound, e.g. modulo or circular addressing
STREAMING ENGINE WITH MULTI DIMENSIONAL CIRCULAR ADDRESSING SELECTABLE AT EACH DIMENSION
#2POWER/AREA EFFICIENT ACCELERATION OF PROCESSOR-BASED ARTIFICIAL NEURAL NETWORK COMPUTATION
#3FETCHING VECTOR DATA ELEMENTS WITH PADDING
#4Streaming engine with multi dimensional circular addressing selectable at each dimension
#5Streaming engine with compressed encoding for loop circular buffer sizes
#6Accelerating processor based artificial neural network computation
#7Automatic address generation for modular electronic devices
#8Streaming engine with compressed encoding for loop circular buffer sizes
#9Streaming engine with multi dimensional circular addressing selectable at each dimension
#10Compression/decompression instruction specifying a history buffer to be used in the compression/decompression of data
#11Vector generating instruction for generating a vector comprising a sequence of elements that wraps as required
#12Streaming engine with multi dimensional circular addressing selectable at each dimension
#13Streaming engine with compressed encoding for loop circular buffer sizes
#14Strideshift instruction for transposing bits inside vector register
#15Secure control flow prediction
#16Cyclic buffer pointer fixing
#17Streaming engine with compressed encoding for loop circular buffer sizes
#18Processor prefetch throttling based on short streams
#19System and method for modulo addressing vectorization with invariant code motion
#20Single instruction array index computation
#21Systems and methods for high speed remote change data capture
#22Method and apparatus for quadrature mirror filtering
#23ARITHMETIC PROCESSING UNIT
#24Data processing apparatus and method for decoding program instructions in order to generate control signals for processing circuitry of the data processing apparatus
#25Data management for image processing
#26Prioritized assignment of sub-range registers of circularly addressable extended register file to loop variables in RISC processor
#27Integrated circuit with control node circuitry and processing circuitry
#28Single instruction group information processing apparatus for dynamically performing transient processing associated with a repeat instruction
#29Address generation
#30Provision of extended addressing modes in a single instruction multiple data (SIMD) data processor
#31Microcomputer and encoding system for executing peripheral function instructions
#32Method for implementing a bit-reversed increment in a data processing system
#33Circular buffer support in a single instruction multiple data (SIMD) data processor
#34PROCESSOR WITH ADDRESS GENERATOR
#35Address generation for quadratic permutation polynomial interleaving
#36Microcomputer
#37Data management for image processing
#38Modulo arithmetic
#39Register allocation method and system for program compiling
#40Integrated data processor
#41Pointer computation method and system for a scalable, programmable circular buffer
#42Lookup table addressing system and method
#43Microcomputer
#44Microcomputer and encoding system for instruction code and CPU
#45Microprocessor instruction using address index values to enable access of a virtual buffer in circular fashion
#46Non-sequential access pattern based address generator