189754 ⎘
Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs; Arrangements for executing machine instructions, e.g. instruction decode; Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes; Indexed addressing, i.e. using more than one address operand using program counter as base address
MULTI-TAKEN PREDICTION ENTRIES FOR PREDICTION RESUMPTION
#2Capability-generating address calculating instruction
#3METHOD FOR PATCHING CHIP AND CHIP
#4Hardware-implemented universal floating-point instruction set architecture for computing directly with human-readable decimal character sequence floating-point representation operands
#5Fully pipelined hardware operator logic circuit for converting human-readable decimal character sequence floating-point representations to IEEE 754-2008 binary floating-point format representations
#6Program counter (PC)-relative load and store addressing for fused instructions
#7Apparatus and method for generating intermediate layer values in parallel
#8Reduced instruction set processor based on memristor
#9Universal floating-point instruction set architecture for computing directly with decimal character sequences and binary formats in any combination
#10Apparatus and method for interpreting permissions associated with a capability
#11Apparatus and methods for matrix multiplication
#12Predicting a table of contents pointer value responsive to branching to a subroutine
#13Predicting a table of contents pointer value responsive to branching to a subroutine
#14Predicting a table of contents pointer value responsive to branching to a subroutine
#15Secure communication between operating system and processes
#16Apparatus and methods for matrix multiplication
#17Implementing a received add program counter immediate shift (ADDPCIS) instruction using a micro-coded or cracked sequence
#18Implementing a received add program counter immediate shift (ADDPCIS) instruction using a micro-coded or cracked sequence
#19MULTI-NULLIFICATION
#20Processor prefetch throttling based on short streams
#21PC-relative addressing and transmission
#22Implementing a received add program counter immediate shift (ADDPCIS) instruction using a micro-coded or cracked sequence
#23Implementing a received add program counter immediate shift (ADDPCIS) instruction using a micro-coded or cracked sequence
#24Extending data range addressing
#25Extending data range addressing
#26Debug support for block-based processor
#27Instruction block address register
#28Prefetching instruction blocks
#29Broadcast channel architectures for block-based processors
#30Block-based processor including topology and control registers to indicate resource sharing and size of logical processor
#31Write nullification
#32Implicit program order
#33Register read/write ordering
#34Dynamic generation of null instructions
#35Generation and use of memory access instruction order encodings
#36Multimodal targets in a block-based processor
#37Dense read encoding for dataflow ISA
#38Distinct system registers for logical processors
#39Block-based processor core composition register
#40Initiating instruction block execution using a register access instruction
#41Method and apparatus for a self-clocked, event triggered superscalar processor
#42Single instruction array index computation
#43Relative offset branching in a fixed-width reduced instruction set computing architecture
#44Absolute address branching in a fixed-width reduced instruction set computing architecture
#45Computer accelerator system using a trigger architecture memory access processor
#46Processor supporting arithmetic instructions with branch on overflow and methods
#47Address generation in a data processing apparatus
#48Executing instructions for managing constant pool base register used for accessing constants during subroutine execution
#49Address generation in a data processing apparatus
#50Data processing apparatus with instruction encodings to enable near and far memory access modes
#51MICROCOMPUTER AND DIVIDING CIRCUIT
#52Load Relative and Store Relative Facility and Instructions Therefore
#53Compare Relative Long Facility and Instructions Therefore
#54MICROCOMPUTER AND DIVIDING CIRCUIT
#55Data access handling in a data processing system
#56Microcomputer and dividing circuit