ATOMIC COMPARE AND SWAP USING MICRO-OPERATIONS

Method and Apparatus for Configuring a Reduced Instruction Set Computer Processor Architecture to Execute a Fully Homomorphic Encryption Algorithm

Systems and Methods to Provide Instructions to Coprocessors

APPARATUS AND METHOD

DECODING METHOD OF SIMULTANEOUSLY MULTI-THREADING PROCESSOR, PROCESSOR, AND CHIP

DATA PIPELINE CONTROLLER

Method and Apparatus for Configuring a Reduced Instruction Set Computer Processor Architecture to Execute a Fully Homomorphic Encryption Algorithm

Scalable toggle point control circuitry for a clustered decode pipeline

Methods and apparatus for context switching

Creation of message serializer for event streaming platform

Method and apparatus for configuring a reduced instruction set computer processor architecture to execute a fully homomorphic encryption algorithm

Information-unit based scaling of an ordered event stream

Vector processor supporting linear interpolation on multiple dimensions

Look-ahead staging for time-travel reconstruction

Detecting a repetitive pattern in an instruction pipeline of a processor to reduce repeated fetching

Controller area network apparatus

Determining prefetch patterns with discontinuous strides

Automatically introducing register dependencies to tests

Accelerating AI training by an all-reduce process with compression over a distributed system

Data pipeline controller

Modifying a series of lock acquire and release operations to use a single lock reservation

SYSTEM AND METHOD FOR GENERATING DATA-FLOW ANALYSIS PIPELINES

Dynamic hammock branch training for branch hammock detection in an instruction stream executing in a processor

PROGRAMMABLE ELECTRONIC DEVICES AND METHODS OF OPERATING THEREOF

Protection domains for processes in shared address space

Instruction fusion using dependence analysis

Method, a device, and a computer program product for determining a resource required for executing a code segment

Method and apparatus for configuring a reduced instruction set computer processor architecture to execute a fully homomorphic encryption algorithm

Apparatus and method for maintaining prediction performance metrics for prediction components for each of a plurality of execution regions and implementing a prediction adjustment action based thereon

Microprocessor, power supply control IC, and power supply

Instruction generation process multiplexing method and device

PROVIDING EARLY PIPELINE OPTIMIZATION OF CONDITIONAL INSTRUCTIONS IN PROCESSOR-BASED SYSTEMS

Processor prefetch throttling based on short streams

MICRO-OP FUSION FOR NON-ADJACENT INSTRUCTIONS

Fused adjacent memory stores

Annotation logic for dynamic instruction lookahead distance determination

MFENCE AND LFENCE MICRO-ARCHITECTURAL IMPLEMENTATION METHOD AND SYSTEM

Loop code processor optimizations

Selective flushing of instructions in an instruction pipeline in a processor back to an execution-resolved target address, in response to a precise interrupt

Processor instruction sequence translation

Processor instruction sequence translation

Last branch record indicators for transactional memory

INSTRUCTION AND LOGIC TO PERFORM A VECTOR SATURATED DOUBLEWORD/QUADWORD ADD

Supporting large pages in hardware prefetchers

Instruction and logic for support of code modification

Filtering out redundant software prefetch instructions

Method and apparatus for precalculating a direct branch partial target address during a misprediction correction process

SYSTEMS AND METHOD FOR UNBLOCKING A PIPELINE WITH SPONTANEOUS LOAD DEFERRAL AND CONVERSION TO PREFETCH

Software license management

Workflow decision management with workflow administration capacities

MFENCE and LFENCE micro-architectural implementation method and system

MFENCE and LFENCE micro-architectural implementation method and system

PREDICATED ISSUE FOR CONDITIONAL BRANCH INSTRUCTIONS

MFENCE and LFENCE micro-architectural implementation method and system

Translated memory protection apparatus for an advanced microprocessor

Consistency checking of source instruction to execute previously translated instructions between copy made upon occurrence of write operation to memory and current version

Processor with last branch record register storing transaction indicator

VERIFICATION OF PROCESSOR ARCHITECTURES ALLOWING FOR SELF MODIFYING CODE

Managing cache coherency for self-modifying code in an out-of-order execution system

Software license management

Translated memory protection

System and Method for Detecting and Recovering from Errors in an Instruction Stream of an Electronic Data Processing System

Handling debugger breakpoints in a shared instruction system

Processor and prefetch support program

Method and system for handling cache coherency for self-modifying code

Coherent instruction cache utilizing cache-op execution resources

Checking for instruction invariance to execute previously obtained translation code by comparing instruction to a copy stored when write operation to the memory portion occur

Processing of self-modifying code in multi-address-space and multi-processor systems

Minimizing unscheduled D-cache miss pipeline stalls in a cascaded delayed execution pipeline

Dynamic instruction and data updating architecture

Double-Width Instruction Queue for Instruction Execution

Predicated issue for conditional branch instructions

Suppression of store checking

Scheduling instructions in a cascaded delayed execution pipeline to minimize pipeline stalls caused by a cache miss

Workflow decision management with workflow administration capacities

Memory caching in data processing

Branch prediction using precedent instruction address of relative offset determined based on branch type and enabling skipping

Processing of self-modifying code in multi-address-space and multi-processor systems

Method and apparatus for redirection of operations between interfaces

Systems and methods for optimizing authentication branch instructions