189779 ⎘
Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs; Arrangements for executing machine instructions, e.g. instruction decode; Concurrent instruction execution, e.g. pipeline, look ahead; Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution; Speculative instruction execution using hybrid branch prediction, e.g. selection between prediction techniques
BRANCH PREDICTOR
#2MACHINE LEARNING FOR BRANCH ANALYSIS
#3BRANCH PREDICTION CORRECTION BASED ON NONUSE OF RELEVANT PREDICTION STRUCTURE
#4FETCH BLOCK-BASED BRANCH PREDICTION
#5SWITCHING A PREDICTED BRANCH TYPE FOLLOWING A MISPREDICTION OF A NUMBER OF LOOP ITERATIONS
#6DEVICE, METHOD AND SYSTEM TO PROVIDE PREDICTION STATE INFORMATION OF A PROCESSOR
#7REDUCED POWER CONSUMPTION PREDICTION USING PREDICTION TABLES
#8COMBINER CACHE STRUCTURE
#9MULTI-LEVEL HYBRID ALGORITHM FILTERING-TYPE BRANCH PREDICTION METHOD AND PREDICTION SYSTEM
#10METHOD AND APPARATUS TO IMPLEMENT ADAPTIVE BRANCH PREDICTION THROTTLING
#11Conditional Instructions Prediction
#12EVENT PATTERN PREDICTION
#13Arithmetic processing device and arithmetic processing method
#14Method for improving accuracy of loop branch prediction
#15Re-enabling use of prediction table after execution state switch
#16INSTRUCTION PREDICTION METHOD AND APPARATUS, SYSTEM, AND COMPUTER-READABLE STORAGE MEDIUM
#17METHOD AND APPARATUS FOR A SCALABLE MICROPROCESSOR WITH TIME COUNTER
#18Branch prediction using hypervectors
#19Hybrid parallelized tagged geometric (TAGE) branch prediction
#20Conditional instructions prediction
#21Register scoreboard for a microprocessor with a time counter for statically dispatching instructions
#22DEVICE, METHOD, AND SYSTEM TO FACILITATE IMPROVED BANDWIDTH OF A BRANCH PREDICTION UNIT
#23Performing branch predictor training using probabilistic counter updates in a processor
#24Program flow prediction for loops
#25Responding to branch misprediction for predicated-loop-terminating branch instruction
#26Neuron cache-based hardware branch prediction
#27COUNT TO EMPTY FOR MICROARCHITECTURAL RETURN PREDICTOR SECURITY
#28Circuitry and method
#29Spectre fixes with indirect valid table
#30Small branch predictor escape
#31Dual branch execute and table update with single port
#32Quick predictor override and update by a BTAC
#33Advanced processor architecture
#34Selective prediction based on correlation between a given instruction and a subset of a set of monitored instructions ordinarily used to generate predictions for that given instruction
#35Microprocessor with multi-step ahead branch predictor and having a fetch-target queue between the branch predictor and instruction cache
#36Flushing in a microprocessor with multi-step ahead branch predictor and a fetch target queue
#37Microprocessor with instruction fetching failure solution
#38Detecting misprediction when an additional branch direction prediction determined using value prediction is considered more accurate than an initial branch direction prediction
#39Indirect branch predictor based on register operands
#40Indirect branch predictor for dynamic indirect branches
#41Prefetch filter table for storing moderately-confident entries evicted from a history table
#42Efficient load value prediction
#43Hybrid and aggregrate branch prediction system with a tagged branch orientation predictor for prediction override or pass-through
#44Secure predictors for speculative execution
#45System, apparatus and method for context-based override of history-based branch predictions
#46Gating updates to branch predictors to reduce pollution from infrequently executed branches
#47Loop exit predictor
#48Selectively supporting static branch prediction settings only in association with processor-designated types of instructions
#49Adaptive utilization mechanism for a first-line defense branch predictor
#50Tagged indirect branch predictor (TIP)
#51Apparatus and method for maintaining prediction performance metrics for prediction components for each of a plurality of execution regions and implementing a prediction adjustment action based thereon
#52Branch target buffer for emulation environments
#53Caching override indicators for statistically biased branches to selectively override a global branch predictor
#54Apparatuses and methods for dynamic asymmetric scaling of branch predictor tables
#55Branch prediction circuitry comprising a return address prediction structure and a branch target buffer structure
#56Branch confidence throttle
#57Arithmetic processing apparatus which replaces values for future branch prediction upon wrong branch prediction
#58Branch prediction structure indexed based on return address popped from a call-return stack
#59Apparatus and method for performing branch prediction using loop minimum iteration prediction
#60Automatic predication of hard-to-predict convergent branches
#61TAGE branch predictor with perceptron predictor as fallback predictor
#62Saving and restoring branch prediction state
#63Apparatus and method for controlling branch prediction
#64System and method for multi-level classification of branches
#65System, apparatus and method for controlling allocations into a branch prediction circuit of a processor
#66Methods for partially preserving a branch predictor state
#67Indirect target tagged geometric branch prediction using a set of target address pattern data
#68SYSTEM AND METHOD FOR MULTIPLEXING VECTOR COMPARE
#69Indexing entries of a storage structure shared between multiple threads
#70Training and utilization of neural branch predictor
#71Providing variable interpretation of usefulness indicators for memory tables in processor-based systems
#72HYBRID FAST PATH FILTER BRANCH PREDICTOR
#73Reduced logic level operation folding of context history in a history register in a prediction system for a processor-based system
#74METHOD AND APPARATUS FOR BRANCH PREDICTION UTILIZING PRIMARY AND SECONDARY BRANCH PREDICTORS
#75Branch destination prediction based on accord or discord of previous load data from a data cache line corresponding to a load instruction and present load data
#76MULTI-NULLIFICATION
#77Indirect target tagged geometric branch prediction using a set of target address pattern data
#78Indirect target tagged geometric branch prediction using a set of target address pattern data
#79Branch predictor selection management
#80Misprediction-triggered local history-based branch prediction
#81Method and apparatus for augmentation and disambiguation of branch history in pipelined branch predictors
#82Power management of branch predictors in a computer processor
#83Heuristic method to control fetching of metadata from a cache hierarchy
#84Branch predictor with empirical branch bias override
#85Branch predictor search qualification using stream length prediction
#86Efficient random number generation for update events in multi-bank conditional branch predictor
#87Energy-focused compiler-assisted branch prediction
#88Selectively blocking branch prediction for a predetermined number of instructions
#89Selectively blocking branch prediction for a predetermined number of instructions
#90Instruction predecoding
#91Method for reducing fetch cycles for return-type instructions
#92Method and device for determining branch prediction history for branch prediction by partially combining shifted branch prediction history with branch signature
#93Advanced processor architecture
#94Indirect branch prediction
#95Stream based branch prediction index accelerator for multiple stream exits
#96Stream based branch prediction index accelerator for multiple stream exits
#97Power management of branch predictors in a computer processor
#98Power management of branch predictors in a computer processor
#99Operation of a multi-slice processor implementing tagged geometric history length (TAGE) branch prediction
#100INSTRUCTION SEQUENCE BUFFER TO STORE BRANCHES HAVING RELIABLY PREDICTABLE INSTRUCTION SEQUENCES
#101Hybrid polymorphic inline cache and branch target buffer prediction units for indirect branch prediction for emulation environments
#102Software-assisted instruction level execution preemption
#103Software-assisted instruction level execution preemption
#104Branch prediction in a computer processor
#105Method and system of gesture recognition in touch display device
#106Debug support for block-based processor
#107Instruction block address register
#108Prefetching instruction blocks
#109Broadcast channel architectures for block-based processors
#110Block-based processor including topology and control registers to indicate resource sharing and size of logical processor
#111Multi-nullification
#112Write nullification
#113Store nullification in the target field
#114Implicit program order
#115Register read/write ordering
#116Dynamic generation of null instructions
#117Generation and use of memory access instruction order encodings
#118Multimodal targets in a block-based processor
#119Dense read encoding for dataflow ISA
#120Distinct system registers for logical processors
#121Block-based processor core composition register
#122Initiating instruction block execution using a register access instruction
#123Branch prediction using multiple versions of history data
#124Branch prediction using multiple versions of history data
#125Variable updates of branch prediction states
#126Mode switching in dependence upon a number of active threads
#127Branch prediction
#128System and method for supporting representational state transfer services natively in a service bus runtime
#129History buffer with hybrid entry support for multiple-field registers
#130System and method for mitigating the impact of branch misprediction when exiting spin loops
#131Variable updates of branch prediction states
#132Hybrid polymoprhic inline cache and branch target buffer prediction units for indirect branch prediction for emulation environments
#133Branch prediction suppression for blocks of instructions predicted to not include a branch instruction
#134Energy-focused compiler-assisted branch prediction
#135Branch prediction using multi-way pattern history table (PHT) and global path vector (GPV)
#136Conditional branch prediction using a long history
#137Apparatus and method for bias-free branch prediction
#138Predicting indirect branches using problem branch filtering and pattern cache
#139Branch prediction using multiple versions of history data
#140Method and system for determining instruction conflict states for issuance of memory instructions in a VLIW processor
#141Computer processor with generation renaming
#142System and method for branch prediction using two branch history tables and presetting a global branch history register
#143Allocating resources to threads based on speculation metric
#144Variable updates of branch prediction states
#145Hybrid bit-sliced dictionary encoding for fast index-based operations
#146Speculative history forwarding in overriding branch predictors, and related circuits, methods, and computer-readable media
#147Fractional use of prediction history storage for operating system routines
#148Bandwidth increase in branch prediction unit and level 1 instruction cache
#149Arithmetic processing device and control method of arithmetic processing device
#150Global branch prediction using branch and fetch group history
#151Global branch prediction using branch and fetch group history
#152Selective accumulation and use of predicting unit history
#153Next fetch predictor return address stack
#154Indirect branch prediction
#155Method and apparatus for branch prediction
#156Thread selection at a processor based on branch prediction confidence
#157Usefulness indication for indirect branch prediction training
#158Energy-focused compiler-assisted branch prediction
#159Using a plurality of tables for improving performance in predicting branches in processor instructions
#160Instruction and logic for optimization level aware branch prediction
#161Branch predictor for wide issue, arbitrarily aligned fetch that can cross cache line boundaries
#162Global weak pattern history table filtering
#163Instruction sequence buffer to store branches having reliably predictable instruction sequences
#164Swapping branch direction history(ies) in response to a branch prediction table swap instruction(s), and related systems and methods
#165Hybrid polymorphic inline cache and branch target buffer prediction units for indirect branch prediction for emulation environments
#166Meta predictor restoration upon detecting misprediction
#167Prediction optimizations for Macroscalar vector partitioning loops
#168Managed instruction cache prefetching
#169Qualifying Software Branch-Target Hints with Hardware-Based Predictions
#170Selectively blocking branch prediction for a predetermined number of instructions
#171Selectively blocking branch prediction for a predetermined number of instructions
#172Mitigating instruction prediction latency with independently filtered presence predictors
#173Global weak pattern history table filtering
#174BRANCH MISPREDICTION BEHAVIOR SUPPRESSION USING A BRANCH OPTIONAL INSTRUCTION
#175Multi level indirect predictor using confidence counter and program counter address filter scheme
#176Selective suppression of branch prediction in vector partitioning loops until dependency vector is available for predicate generating instruction
#177System and method for mitigating the impact of branch misprediction when exiting spin loops
#178System and method for selectively saving and restoring state of branch prediction logic through separate hypervisor-mode and guest-mode and/or user-mode instructions
#179Virtualization support for branch prediction logic enable / disable at hypervisor and guest operating system levels
#180Preventing update training of first predictor with mismatching second predictor for branch instructions with alternating pattern hysteresis
#181Software-assisted instruction level execution preemption
#182Processor and control method of processor
#183PROCESSOR AND CONTROL METHOD OF PROCESSOR
#184Meta predictor restoration upon detecting misprediction
#185Processor and data processing method incorporating an instruction pipeline with conditional branch direction prediction for fast access to branch target instructions
#186Performance in predicting branches
#187LOW-LATENCY BRANCH TARGET CACHE
#188PREDICATED ISSUE FOR CONDITIONAL BRANCH INSTRUCTIONS
#189Combined level 1 and level 2 branch predictor
#190Power efficient pattern history table fetch in branch predictor
#191Detecting branch direction and target address pattern and supplying fetch address by replay unit instead of branch prediction unit
#192INDIRECT BRANCH PREDICTION BASED ON BRANCH TARGET BUFFER HYSTERESIS
#193System and method for selectively managing a branch target address cache of a multiple-stage predictor
#194Operating system aware branch predictor using a dynamically reconfigurable branch history table
#195State machine-based filtering of pattern history tables based on distinguishable pattern detection
#196Indirect branch target predictor that prevents speculation if mispredict is expected
#197Executing touchBHT instruction to pre-fetch information to prediction mechanism for branch with taken history
#198Branch target buffer for emulation environments
#199Perceptron-based branch prediction mechanism for predicting conditional branch instructions on a multithreaded processor
#200BRANCH PREDICTION MECHANISM FOR PREDICTING INDIRECT BRANCH TARGETS
#201Predictors with adaptive prediction threshold
#202Branch prediction path wrong guess instruction
#203System and method for repairing a speculative global history record
#204System and method for a multi-schema branch predictor
#205Control-flow prediction using multiple independent predictors
#206System and method for branch misprediction prediction using a mispredicted branch table having entry eviction protection
#207Microprocessor system for simultaneously accessing multiple branch history table entries using a single port
#208Branch prediction mechanisms using multiple hash functions
#209Method and system for power conservation in a hierarchical branch predictor
#210Method and system for purging pattern history tables as a function of global accuracy in a state machine-based filtered gshare branch predictor
#211Mitigating lookahead branch prediction latency by purposely stalling a branch instruction until a delayed branch prediction is received or a timeout occurs
#212Global history branch prediction updating responsive to taken branches
#213Branch prediction with partially folded global history vector for reduced XOR operation time
#214Indexed table circuit having reduced aliasing
#215Branch history with polymorphic indirect branch information
#216Local and global branch prediction information storage
#217System and method for speculative global history prediction updating
#218Structure for predictive decoding
#219Branch predictor for branches with asymmetric penalties
#220Branch target address cache
#221Branch prediction device and method that breaks accessing a pattern history table into multiple pipeline stages
#222Target branch prediction using a plurality of tables
#223METHODS AND APPARATUS FOR IMPLEMENTING POLYMORPHIC BRANCH PREDICTORS
#224Method for predictive decoding of a load tagged pointer instruction
#225Method, system, and computer program product for path-correlated indirect address predictions
#226Data processor and memory read active control method
#227DESIGN STRUCTURE FOR DOUBLE-WIDTH INSTRUCTION QUEUE FOR INSTRUCTION EXECUTION
#228System and method for using a working global history register
#229Predicting instruction branches with bimodal, little global, big global, and loop (BgGL) branch predictors
#230Overriding a static prediction with a level-two predictor
#231Filtered branch-prediction predicate generation
#232Hybrid branch predictor having negative ovedrride signals
#233Associate Cached Branch Information with the Last Granularity of Branch instruction in Variable Length instruction Set
#234System and method for selectively managing a branch target address cache of a multiple-stage predictor
#235Polymorphic branch predictor and method with selectable mode of prediction
#236Local and global branch prediction information storage
#237Branch prediction within a multithreaded processor
#238Double-Width Instruction Queue for Instruction Execution
#239Hybrid Branch Prediction Scheme
#240Dual Path Issue for Conditional Branch Instructions
#241Predicated issue for conditional branch instructions
#242System for target branch prediction using correlation of local target histories including update inhibition for inefficient entries
#243Representing loop branches in a branch history register with multiple bits
#244Information processing apparatus, replacing method, and computer-readable recording medium on which a replacing program is recorded
#245Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequence
#246Hybrid branch predictor using component predictors each having confidence and override signals
#247Branch predictor for a processor and method of predicting a conditional branch
#248Branch prediction apparatus, its method and processor
#249Reading prediction outcomes within a branch prediction mechanism
#250System for speculative branch prediction optimization and method thereof
#251Branch target address cache storing two or more branch target addresses per index
#252Method and system for branch prediction
#253Pipeline having bifurcated global branch history buffer for indexing branch history table per instruction fetch group
#254Branch prediction of unconditionally executed branch instructions
#255Controller for instruction cache and instruction translation look-aside buffer, and method of controlling the same
#256Processes, circuits, devices, and systems for branch prediction and other processor improvements
#257Information processing apparatus, method, and computer-readable recording medium for replacing an entry in a memory device
#258Branch prediction and other processor improvements using FIFO for bypassing certain processor pipeline stages
#259Method for executing structured symbolic machine code on a microprocessor
#260Prophet/critic hybrid predictor
#261Run-time updating of prediction hint instructions
#262Loop end prediction
#263Method and structure for concurrent branch prediction in a processor
#264Method and system for branch target prediction using path information
#265State machine based filtering of non-dominant branches to use a modified gshare scheme
#266Branch prediction mechanism using multiple hash functions
#267Method and apparatus for predicting confidence and value
#268Energy-focused compiler-assisted branch prediction
#269Predicting instruction branches with a plurality of global predictors using varying amounts of history instruction
#270Speculative hybrid branch direction predictor
#271Predicting instruction branches with independent checking predictions
#272Method and apparatus for prediction handling multiple branches simultaneously
#273Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequence
#274Branch prediction apparatus and method for low power consumption
#275Recovery of global history vector in the event of a non-branch flush
#276Two-bit branch prediction scheme using reduced memory size
#277Prediction unit with first predictor that provides a hashed fetch address of a current fetch block to its own input and to a second predictor that uses it to predict the fetch address of a next fetch block
#278Multi-degree branch predictor
#279Suppressing pipeline redirection indications
#280Auxiliary perceptron branch predictor with magnitude usage limit