189792 ⎘
Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs; Arrangements for executing machine instructions, e.g. instruction decode; Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines Pipelining a single stage, e.g. superpipelining
INTENT-BASED ORCHESTRATION IN HETEROGENOUS COMPUTE PLATFORMS
#2DEVICE FOR PROCESSING HOMOMORPHICALLY ENCRYPTED DATA
#3FLOATING-POINT SUPPORTIVE PIPELINE FOR EMULATED SHARED MEMORY ARCHITECTURES
#4Intent-based orchestration in heterogenous compute platforms
#5SYSTEMS AND METHODS FOR REACTIVE INTENT-DRIVEN END-TO-END ORCHESTRATION
#6INTENT-BASED CLUSTER ADMINISTRATION
#7COMPUTATIONAL STORAGE IN A FUNCTION-AS-A-SERVICE ARCHITECTURE
#8INTENT-DRIVEN POWER MANAGEMENT
#9Exception register delay
#10INFORMATION PROCESSING SYSTEM, METHOD OF PROCESSING INFORMATION, AND INFORMATION PROCESSING APPARATUS
#11Configurable pipeline based on error detection mode in a data processing system
#12Method and apparatus for efficient scheduling for asymmetrical execution units
#13Run-Time Parallelization of Code Execution Based on an Approximate Register-Access Specification
#14Managing a free list of resources to decrease control complexity and reduce power consumption
#15Run-time parallelization of code execution based on an approximate register-access specification
#16System and method for pipeline management of artifacts
#17Floating-point supportive pipeline for emulated shared memory architectures
#18Managing history information for branch prediction
#19Selectively performing a single cycle write operation with ECC in a data processing system
#20Utilizing pipeline registers as intermediate storage
#21On-the-fly conversion during load/store operations in a vector processor
#22Data processing apparatus and method for performing scan operations
#23Apparatus and method for controlling the number of vector elements written to a data store while performing speculative vector write operations
#24Method and apparatus for efficient scheduling for asymmetrical execution units
#25Data processing apparatus having a parallel processing circuit including a plurality of processing modules, and method for controlling the same
#26Automatic pipeline stage insertion
#27Division unit with normalization circuit and plural divide engines for receiving instructions when divide engine availability is indicated
#28Apparatus for switching a plurality of ALUs between tree and cascade configurations
#29Multi-level instruction cache prefetching
#30Processing core with speculative register preprocessing in unused execution unit cycles
#31Executing misaligned load dependent instruction in second execution stage in parity protected mode in configurable pipelined processor
#32Data processing apparatus having a parallel processing circuit including a plurality of processing modules, and method for controlling the same
#33MULTIPROCESSOR
#34MICROPROCESSOR HAVING AT LEAST ONE APPLICATION SPECIFIC FUNCTIONAL UNIT AND METHOD TO DESIGN SAME
#35Microprocessor with ALU integrated into store unit
#36Microprocessor with ALU integrated into load unit
#37Serial flash memory and address transmission method thereof
#38Result forwarding to dependent instruction in pipelined processor with mode selectable execution in E1 or E2 of pipelined operational stages
#39PROCESSOR SYSTEM EXECUTING PIPELINE PROCESSING AND PIPELINE PROCESSING METHOD
#40Method of Performing Serial Functions in Parallel
#41APPARATUS COMPRISING A PLURALITY OF ARITHMETIC LOGIC UNITS
#42Address generation
#43Processor having ALU with dynamically transparent pipeline stages
#44Microprocessor with highly configurable pipeline and executional unit internal hierarchal structures, optimizable for different types of computational functions
#45Configurable pipeline to process an operation at alternate pipeline stages depending on ECC/parity protection mode of memory access
#46Multithreaded processor with fast and slow paths pipeline issuing instructions of differing complexity of different instruction set and avoiding collision
#47Serial data processing circuit
#48Reducing errors in pre-decode caches
#49Method and apparatus for a double width load using a single width load port
#50INFORMATION PROCESSING DEVICE
#51Pre-fetch circuit of semiconductor memory apparatus and control method of the same
#52Computation parallelization in software reconfigurable all digital phase lock loop
#53Inter-cluster communication network and heirarchical register files for clustered VLIW processors
#54High Frequency Stall Design
#55Hierarchical instruction scheduler facilitating instruction replay
#56Data processing apparatus of high speed process using memory of low speed and low power consumption
#57Relative address generation
#58Run length encoding in VLIW architecture
#59Microprocessor system and method for instruction-initiated recording and execution of instruction sequences in a dynamically decoupleable extended instruction pipeline
#60Parameterizable clip instruction and method of performing a clip operation using the same
#61Systems and methods for selectively decoupling a parallel extended instruction pipeline
#62Systems and methods for synchronizing multiple processing engines of a microprocessor
#63System and methods for performing deblocking in microprocessor-based video codec applications
#64Systolic-array based systems and methods for performing block matching in motion compensation
#65Systems and methods for accelerating sub-pixel interpolation in video processing applications
#66System and method for high frequency stall design
#67Data processor
#68Address generation unit with operand recycling
#69Converting a processor into a compatible virtual multithreaded processor (VMP)
#70High performance architecture for a writeback stage
#71Method and system for pipelining saturated accumulation and other loops with loop-carried dependencies
#72Handling cache miss in an instruction crossing a cache line boundary
#73Controlling out of order execution pipelines issue tagging
#74Method and virtual port register array for implementing shared access to a register array port by multiple sources
#75Data processing apparatus and method for executing a sequence of instructions including a multiple iteration instruction
#76Method and apparatus to execute an instruction with a semi-fast operation in a staggered ALU
#77Re-configurable circuit and configuration switching method
#78Decoding predication instructions within a superscaler data processing system
#79Method and apparatus for power reduction utilizing heterogeneously-multi-pipelined processor
#80Method in pipelined data processing
#81Processing activity masking in a data processing system
#82Encoding method for very long instruction word (VLIW) DSP processor and decoding method thereof
#83Processing activity masking in a data processing system
#84Multipurpose functional unit with combined integer and floating-point multiply-add pipeline
#85Multipurpose functional unit with multiplication pipeline, addition pipeline, addition pipeline and logical test pipeline capable of performing integer multiply-add operations
#86Multi-purpose floating point and integer multiply-add functional unit with multiplication-comparison test addition and exponent pipelines
#87Branch prediction and other processor improvements using FIFO for bypassing certain processor pipeline stages
#88Processing activity masking in a data processing system
#89Variable cycle instruction execution in variable or maximum fixed cycle mode to disguise execution path
#90Method and apparatus for staggering execution of an instruction
#91Executing partial-width packed data instructions
#92Digital signal processors with configurable dual-MAC and dual-ALU
#93Half-rate clock logic block and method for forming same