ClassID:

196250

G09G2360/123 - CPC Classification

Classification description:

Aspects of the architecture of display systems; Frame memory handling using interleaving

Recent Application in this class:
#1
20240371342
2024-11-07

BIT PLANE DITHERING APPARATUS

#2
20240331659
2024-10-03

POWER MANAGEMENT OF DISPLAY DATA DURING AN IDLE SCREEN

#3
20240329720
2024-10-03

STORING CONTIGUOUS DISPLAY CONTENT IN EACH DRAM FOR IDLE STATIC SCREEN POWER SAVING

#4
20240071308
2024-02-29

DISPLAY DEVICE AND PIXEL CIRCUIT THEREOF

#5
20230274719
2023-08-31

Bit plane dithering apparatus

#6
20220156876
2022-05-19

Compute optimization mechanism for deep neural networks

#7
20210142767
2021-05-13

Burst image data reading method and apparatus, electronic device, and readable storage medium

#8
20200034946
2020-01-30

Compute optimization mechanism for deep neural networks

#9
20200005426
2020-01-02

Scalable and area efficient conversion of linear image data into multi-dimensional image data for multimedia applications

#10
20190005703
2019-01-03

Automated graphics and compute tile interleave

#11
20180308457
2018-10-25

Frame complexity based dynamic PPI for displays

#12
20180308206
2018-10-25

Compute optimization mechanism for deep neural networks

#13
20180293942
2018-10-11

Apparatus and method for pixel data reordering

#14
20180108331
2018-04-19

Merged access units in frame buffer compression

#15
20170200412
2017-07-13

Display device and pixel circuit thereof

#16
20150026420
2015-01-22

Memory access using address bit permutation

#17
20140075117
2014-03-13

Display pipe alternate cache hint

#18
20130278618
2013-10-24

Method and apparatus for controlling writing of data to graphic memory

#19
20130145107
2013-06-06

Idle power control in multi-display systems

#20
20130100148
2013-04-25

Display controller and display device including the same

#21
20120242670
2012-09-27

Memory system and method for improved utilization of read and write bandwidth of a graphics processing system

#22
20120194530
2012-08-02

Multiple simultaneous unique outputs from a single display pipeline

#23
20120147023
2012-06-14

CACHING APPARATUS AND METHOD FOR VIDEO MOTION ESTIMATION AND COMPENSATION

#24
20120098843
2012-04-26

Apparatus for controlling memory device and related method

#25
20120050811
2012-03-01

Image processing apparatus configured to perform image processing for plural images and control method thereof

#26
20110273462
2011-11-10

System and method for storing and accessing pixel data in a graphics display device

#27
20110169846
2011-07-14

Memory system and method for improved utilization of read and write bandwidth of a graphics processing system

#28
20110090251
2011-04-21

Alpha-to-coverage value determination using virtual samples

#29
20110090250
2011-04-21

Alpha-to-coverage using virtual samples

#30
20110080428
2011-04-07

Image rotation method and apparatus

#31
20100220103
2010-09-02

Memory system and method for improved utilization of read and write bandwidth of a graphics processing system

#32
20100156917
2010-06-24

IMAGE PROCESSING APPARATUS AND METHOD FOR MANAGING FRAME MEMORY IN IMAGE PROCESSING

#33
20100066900
2010-03-18

IMAGE PROCESSING METHOD

#34
20100039560
2010-02-18

Video processing apparatus and method

#35
20100030993
2010-02-04

Memory access control device, method and recording medium for simultaneously accessing horizontally or vertically consecutive unit data or unit data on vertically alternate lines in different modes

#36
20090309889
2009-12-17

Method and apparatus for contolling writing of data to graphic memory

#37
20090256850
2009-10-15

Method for processing display data

#38
20090231351
2009-09-17

SEMICONDUCTOR MEMORY DEVICE HAVING DATA ROTATION/INTERLEAVE FUNCTION

#39
20090189918
2009-07-30

Method and system for fast 90 degree rotation of arrays

#40
20090109784
2009-04-30

Method of accessing synchronous dynamic random access memory, memory control circuit, and memory system including the same

#41
20080253694
2008-10-16

Method and device for processing image data stored in a frame buffer

#42
20080250212
2008-10-09

METHOD AND APPARATUS FOR ACCESSING MEMORY USING PROGRAMMABLE MEMORY ACCESSING INTERLEAVING RATIO INFORMATION

#43
20080218525
2008-09-11

Memory system and method for improved utilization of read and write bandwidth of a graphics processing system

#44
20080211816
2008-09-04

Multiple parallel processor computer graphics system

#45
20080162802
2008-07-03

Accessing memory using multi-tiling

#46
20080122855
2008-05-29

Semiconductor integrated circuit device for display controller

#47
20070176881
2007-08-02

Driving circuit for driving liquid crystal display device and method thereof

#48
20070165015
2007-07-19

Efficient use of synchronous dynamic random access memory

#49
20070126747
2007-06-07

Interleaved video frame buffer structure

#50
20060007235
2006-01-12

Method of accessing frame data and data accessing device thereof

#51
20050212808
2005-09-29

Management method and display method of on-screen display thereof and related display controlling device

#52
20050057572
2005-03-17

Checkerboard buffer

#53
20050024368
2005-02-03

Two dimensional buffer pages

#54
20050024367
2005-02-03

Memory system and method for improved utilization of read and write bandwidth of a graphics processing system

#55
13963321
2015-12-22

System performance improvement using data reordering and/or inversion