199488 ⎘
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh
Sub-classes:SYSTEM AND METHOD FOR SOLID STATE MEMORY REFRESH
#2Background reads for solid state storage
#3Semiconductor structure and endurance test method using the same
#4Refresh modes for performing various refresh operation types
#5Refresh of differing capacity NAND
#6Apparatuses, systems, and methods for identifying victim rows in a memory device which cannot be simultaneously refreshed
#7Apparatuses and methods for compute components formed over an array of memory cells
#8Granular refresh rate control for memory devices based on bit position
#9Cycled background reads
#10Apparatuses and methods for compute components formed over an array of memory cells
#11Dynamic memory physical unclonable function
#12Semiconductor device
#13Method for processing blocks of flash memory
#14Apparatuses and methods for compute components formed over an array of memory cells
#15Semiconductor memory device and refresh method of semiconductor memory device
#16Semiconductor device comprising memory cell
#17Methods of retaining and refreshing data in a thyristor random access memory
#18Apparatuses including memory section control circuits with global drivers
#19Memory for storing the number of activations of a wordline, and memory systems including the same
#20Methods of retaining and refreshing data in a thyristor random access memory
#21Semiconductor memory device
#22Techniques for providing a direct injection semiconductor memory device
#23Semiconductor memory device
#24Semiconductor memory device and method for refreshing memory cells
#25Active control device, semiconductor device and system including the same
#26Memory refresh methods, memory section control circuits, and apparatuses
#27SEMICONDUCTOR MEMORY SYSTEM
#28Method, apparatus and system for responding to a row hammer event
#29Self-refresh control device and method for reducing a current requisite for self-refresh operation using the same
#30Refresh control circuit of semiconductor apparatus
#31Bit-line sense amplifier, semiconductor memory device and memory system including the same
#32SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE
#33Memory refresh methods, memory section control circuits, and apparatuses
#34Cell array and memory with stored value update
#35Techniques for providing a direct injection semiconductor memory device
#36Apparatus and method for hidden-refresh modification
#37Methods of operating DRAM devices having adjustable internal refresh cycles that vary in response to on-chip temperature changes
#38Semiconductor memory device that controls refresh period, memory system and operating method thereof
#39Dynamic memory performance throttling
#40Semiconductor memory device
#41Memory device, operation method thereof and memory system having the same
#42Refresh circuits
#43Semiconductor memory device and method for refreshing memory cells
#44Refresh circuit in semiconductor memory device
#45Memory and method of refreshing a memory
#46Refresh circuit of a semiconductor memory device and refresh control method of the semiconductor memory device
#47Semiconductor device having hierarchical bit line structure
#48Techniques for providing a direct injection semiconductor memory device
#49Memory refresh methods, memory section control circuits, and apparatuses
#50Methods of operating DRAM devices having adjustable internal refresh cycles that vary in response to on-chip temperature changes
#51System and method for hidden refresh rate modification
#52Semiconductor device having hierarchical bit line structure
#53Methods of operating DRAM devices having adjustable internal refresh cycles that vary in response to on-chip temperature changes
#54Techniques for providing a direct injection semiconductor memory device
#55Techniques for providing a direct injection semiconductor memory device
#56Techniques for providing a direct injection semiconductor memory device
#57System and method for hidden-refresh rate modification
#58Circuit and method for controlling refresh periods in semiconductor memory devices
#59System and method for hidden-refresh rate modification
#60Intelligent refresh of 3D NAND
#61Simultaneous plural wordline within a bank refreshing control device and memory device including the same
#62Profiling method of address access count of semiconductor device and profiling circuit using the same
#63Semiconductor memory device including refresh control circuit and method of refreshing the same