Periodic calibrations during memory device self refresh

Protocol for refresh between a memory controller and a memory

Memory devices with selective page-based refresh

Dynamic random access memory applied to an embedded display port

Maintenance operations in a DRAM

Protocol for memory power-mode control

Systems and methods for improved error correction in a refreshable memory

Semiconductor devices

Systems and methods for memory cell array initialization

Semiconductor device and method of driving the same

Semiconductor devices and methods of handling data lifetime codes used therein

Semiconductor device, semiconductor system including the same and operating method for a semiconductor system

Semiconductor device and method for controlling a refresh operation and a memory system including the same

Memory device performing care operation for disturbed row and operating method thereof

Apparatuses and methods for detection refresh starvation of a memory

Circuit for selecting row to be refreshed

Reduction of power consumption in memory devices during refresh modes

Non-volatile memory adapted to configure low power dynamic random access memory

Stack refresh control for memory device

Systems and methods for memory cell array initialization

Controller-based memory scrub for DRAMs with internal error-correcting code (ECC) bits contemporaneously during auto refresh or by using masked write commands

Testing and setting performance parameters in a semiconductor device and method therefor

Volatile memory device with automatic lower power state

Power management of memory chips based on working set size

Maintenance operations in a DRAM

Control of refresh operation for first memory region at first frequency and for second memory region at second frequency

Semiconductor memory device

System on chip for reducing wake-up time, method of operating same, and computer system including same

Semiconductor memory device

Quick energy efficient reboot from ultra-low power mode for a system on a chip

Refresh control device with plurality of oscillator circuits

Extending flash storage lifespan and data quality with data retention protection

Apparatus and methods for refreshing memory cells of a semiconductor device

Image forming apparatus and method for controlling image forming apparatus

Refreshing of dynamic random access memory

Apparatuses and methods for refresh control

DRAM having a plurality of registers

Semiconductor device

Vacuum blender

Apparatuses and methods for distributing row hammer refresh events across a memory device

Method of phase calibration for double data rate memory interface and related system

Memory device and refresh method thereof

Semiconductor devices

Oscillator controlled random sampling method and circuit

Memory device for controlling refreshing operation

SYSTEM AND METHOD FOR RETAINING DRAM DATA WHEN REPROGRAMMING RECONFIGURABLE DEVICES WITH DRAM MEMORY CONTROLLERS INCORPORATING A DATA MAINTENANCE BLOCK COLOCATED WITH A MEMORY MODULE OR SUBSYSTEM

Volatile memory device and electronic device comprising refresh information generator, information providing method thereof, and refresh control method thereof

Apparatuses and methods for temperature independent oscillators

Providing State Storage in a Processor for System Management Mode

Information processing apparatus, activation method of information processing apparatus, and storage medium

Memory device having a plurality of low power states

Refresh timing generation circuit, refresh control circuit and semiconductor apparatus with efficient current consumption

Memory device

STAGGERING INITIATION OF REFRESH IN A GROUP OF MEMORY DEVICES

Refresh control device

Memory control circuit and memory controlling method

Memory apparatus including a command controller

Semiconductor device and power distribution network

Polarity based data transfer function for volatile memory

Systems and Methods for Memory Refresh Timing

Temperature-dependent refresh circuit configured to increase or decrease a count value of a refresh timer according to a self-refresh signal

Semiconductor devices

Performance of additional refresh operations during self-refresh mode

Volatile memory, memory module including the same, and method for operating the memory module

Apparatuses and methods for operations in a self-refresh state

Interface device for a data processing system

System for managing memory devices

Directed per bank refresh command

Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements

Using data pattern to mark cache lines as invalid

Oscillator controlled random sampling method and circuit

Apparatuses, methods, and systems for package on package memory refresh and self-refresh rate management

Semiconductor memory device performing refresh operation based on weak cell information stored in memory array region and operating method thereof

Semiconductor device and semiconductor system

Refresh control device with plurality of oscillator circuits

Self refresh state machine MOP array

Periodic ZQ calibration with traffic-based self-refresh in a multi-rank DDR system

Fine granularity refresh

Low power memory throttling

Memory device shared by two or more processors and system including the same

Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements

Memory module, system including the same

DRAM access in self-refresh state

System for data retention and method of operating system

Control module for data retention and method of operating control module

System and method for controlling power consumption

Memory device, refresh method, and system including the same

Memory access method, storage-class memory, and computer system

Apparatuses and methods for refresh control

Memory device and refresh methods to alleviate the effects of row hammer condition

Dynamic rank switching for low power volatile memory

Memory backup management in computing systems

Apparatus and method for implementing a multi-level memory hierarchy

METHODS AND SYSTEMS FOR TRANSITIONING TO AND FROM DIFFERENT STORAGE DEVICE POWER STATES USING HOST MEMORY BUFFER (HMB)

System and method for enhanced security and update of SMM to prevent malware injection

Apparatuses and methods for refreshing memory cells of a semiconductor device

Refresh verification circuit, semiconductor apparatus and semiconductor system

Method for operating the semiconductor device

Volatile memory device and electronic device comprising refresh information generator, information providing method thereof, and refresh control method thereof

Memory device and system including the same

Method of phase calibration for double data rate memory interface and related system

Refresh controller and memory device including the same

Semiconductor memory device for performing refresh operation and operating method therof

Memory device command receiving and decoding methods

System on a chip with always-on processor which reconfigures SOC and supports memory-only communication mode

Reduction of power consumption in memory devices during refresh modes

Performance of additional refresh operations during self-refresh mode

Refresh address controlling scheme based on refresh counter and mask circuit

Method for memory scrub of DRAM with internal error correcting code (ECC) bits during either memory activate and/or precharge operation

Controller-based memory scrub for DRAMs with internal error-correcting code (ECC) bits contemporaneously during auto refresh or by using masked write commands

Method for scrubbing and correcting DRAM memory data with internal error-correcting code (ECC) bits contemporaneously during self-refresh state

Semiconductor device including air spacer

Memory device, refresh method, and system including the same

Controlling a refresh mode of a dynamic random access memory (DRAM) die

DYNAMIC RANDOM ACCESS MEMORY CIRCUIT AND VOLTAGE CONTROLLING METHOD THEREOF

MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME FOR CONTROLLING COLLISION BETWEEN ACCESS OPERATION AND REFRESH OPERATION

Semiconductor device configured to generate a refresh pulse for executing a refresh operation in response to the decoded count signal and temperature code

Memory device and memory system performing request-based refresh, and operating method of the memory device

Memory capable of entering/exiting power down state during self-refresh period and associated memory controller and memory system

Memory device for refresh and memory system including the same

Memory device and system including the same

Protocol for memory power-mode control

System and method for retaining DRAM data when reprogramming reconfigurable devices with DRAM memory controllers incorporating a data maintenance block colocated with a memory module or subsystem

Refresh timer synchronization between memory controller and memory

Semiconductor memory devices including redundancy memory cells

MANAGEMENT OF MEMORY REFRESH POWER CONSUMPTION

Memory device including resistance random access memory, and storing method that stores data in the resistance random access memory

Memory device refresh commands on the fly

Semiconductor devices and semiconductor systems

System and method for controlling power consumption

Method of refreshing memory device

Method and system for analyzing a refresh rate of a volatile memory device

Memory control circuit for controlling memory device that operates in self-refresh mode, and method of controlling the same

Dynamic random access memory device and operating method with improved reliability and reduced cost

Memory systems that adjust an auto-refresh operation responsive to a self-refresh operation history

System and method for reducing power consumption of memory

Maintenance operations in a DRAM

Semiconductor memory device managing flexible refresh skip area

Method and apparatus for completing pending write requests to volatile memory prior to transitioning to self-refresh mode

Smart in-module refresh for DRAM

Memory interface configurable for asynchronous and synchronous operation and for accessing storage from any clock domain

Providing state storage in a processor for system management mode

Flushing and restoring core memory content to external memory

Apparatuses and methods for compute enabled cache

Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements

System on chip for reducing wake-up time, method of operating same, and computer system including same

Multi-level versatile memory

Memory device and memory system including the same

Memory device, and semiconductor device and electronic appliance including the same

Dynamic random access memory with fully independent partial array refresh function

Methods and apparatuses for memory power reduction

METHOD FOR ACCESSING MULTI-PORT MEMORY MODULE, METHOD FOR INCREASING WRITE PORTS OF MEMORY MODULE AND ASSOCIATED MEMORY CONTROLLER

Smart in-module refresh for DRAM

Volatile memory, memory module including the same, and method for operating the memory module

Reduction of power consumption in memory devices during refresh modes

Semiconductor memory device

Apparatuses including memory section control circuits with global drivers

Semiconductor device

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME

Semiconductor memory devices including redundancy memory cells

Memory device and memory system including the same

Maintenance operations in a DRAM

Solid state drive with self-refresh power saving mode

Semiconductor device performing refresh operation and method for driving the same

MEMORY DEVICE FOR PERFORMING INFORMATION TRANSMISSION DURING IDLE PERIOD AND METHOD OF OPERATING THE SAME

System on chip power management

Control apparatus, control method of control apparatus, and storage medium

Memory system including plurality of DRAM devices operating selectively

Information processing apparatus and information processing method

Memory paging for processors using physical addresses

Fast exit from DRAM self-refresh

Semiconductor devices and integrated circuits including the same

Systems and methods involving multi-bank, dual- or multi-pipe SRAMs

Memory device command receiving and decoding methods

Polarity based data transfer function for volatile memory

Multi-channel self refresh device

Leveraging instruction RAM as a data RAM extension during use of a modified Harvard architecture processor

Semiconductor memory device and memory system including same

Semiconductor device

Smart holding registers to enable multiple register accesses

Semiconductor device performing different types of refresh operations and method of driving the same

Method of use time management for semiconductor device and semiconductor device including use time managing circuit

Memory circuit and refresh method thereof

Devices for self-refreshing memories, and methods thereof

Method and apparatus for in-system repair of memory in burst refresh

NONVOLATILE MEMORY MODULE

Memory device and memory system including the same

Synchronizing refresh control circuit for a plurality of slices and semiconductor apparatus using the same

Maintenance operations in a DRAM

Semiconductor device and information processing device

Non-volatile memory with LPDRAM

INDUCED THERMAL GRADIENTS

Fast exit from DRAM self-refresh

Testing and setting performance parameters in a semiconductor device and method therefor

Testing and setting performance parameters in a semiconductor device and method therefor

Testing and setting performance parameters in a semiconductor device and method therefor

EFFICIENT MODIFICATION OF DATA IN NON-VOLATILE MEMORY

Non-volatile memory interface

Method of operating a volatile memory device and a memory controller

Image forming apparatus and method for controlling image forming apparatus

Directed per bank refresh command

Data storage device and operating method thereof

Oscillator and memory device including the same

Flash memory control apparatus utilizing buffer to temporarily storing valid data stored in storage plane, and control system and control method thereof

System and method for retaining dram data when reprogramming reconfigurable devices with DRAM memory controllers incorporating a data maintenance block colocated with a memory module or subsystem

Systems and methods for processing data

Solid state drive and operation method thereof

Memory device, and semiconductor device and electronic appliance including the same

Non-volatile memory validity

Two-stage read/write 3D architecture for memory devices

Application-transparent hybridized caching for high-performance storage

VOLATILE MEMORY, MEMORY MODULE INCLUDING THE SAME, AND METHOD FOR OPERATING THE MEMORY MODULE

Memory access scheme for system on chip

Packet processing apparatus and packet processing method

Apparatuses and methods having memory tier structure and recursively searching between tiers for address in a translation table where information is only directly transferred between controllers

Memory system and control method

Memory module and memory system including the same

Memory systems and methods for dynamically phase adjusting a write strobe and data to account for receive-clock drift

Semiconductor memory device

Storage device for performing in-storage computing operations, method of operation the same, and system including the same

SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME

Semiconductor memory devices including redundancy memory cells

Semiconductor memory device

Management of memory refresh power consumption

RELOCATING INFREQUENTLY-ACCESSED DYNAMIC RANDOM ACCESS MEMORY (DRAM) DATA TO NON-VOLATILE STORAGE

Memory and memory system including the same

Non-volatile random access memory power management using self-refresh commands

Maintenance operations in a DRAM

Semiconductor devices and integrated circuits including the same

Memory and memory system for periodic targeted refresh

Semiconductor memory device and method for operating the same

Semiconductor devices

Semiconductor memory device for use in multi-chip package

Refresh scheme for memory cells with next bit table

Semiconductor memory device capable of preventing negative bias temperature instability (NBTI) using self refresh information

MEMORY, MEMORY SYSTEM INCLUDING THE MEMORY AND METHOD FOR OPERATING THE MEMORY SYSTEM

Partial access mode for dynamic random access memory

Write and read collision avoidance in single port memory devices

Partial access mode for dynamic random access memory

Stack position determination in memory devices configured for stacked arrangements

Method and apparatus for refreshing a memory cell

Memory controller, computing device with a memory controller, and method for calibrating data transfer of a memory system

Semiconductor device, method for controlling the same, and semiconductor system

DEVICE PERFORMING REFRESH OPERATIONS OF MEMORY AREAS

Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements

Protocol for memory power-mode control

Semiconductor devices

Semiconductor device

APPARATUS AND METHOD FOR SELECTING MEMORY OUTSIDE A MEMORY ARRAY

Power control of a plurality of functional units

Protocol for refresh between a memory controller and a memory device

Memory and memory system including the same

MEMORY AND MEMORY SYSTEM INCLUDING THE SAME

Adaptive memory system for enhancing the performance of an external computing device

Memory scheduling method and memory controller

COHERENCE PROCESSING EMPLOYING BLACK BOX DUPLICATE TAGS

Current memory cell and a current mode digital-to-analog converter including the same

Method of refreshing volatile memory device

Memory device, memory system and operating method thereof

Memory device having adjustable refresh period and method of operating the same

Communication apparatus and data processing method

Automatic partial array self-refresh

IC card and IC card system having suspend/resume functions

Valid command detection based on stack position identifiers in memory devices configured for stacked arrangements

Latency adjustment based on stack position identifier in memory devices configured for stacked arrangements

Memory devices with serially connected signals for stacked arrangements

Pad selection in memory devices configured for stacked arrangements

Self-refresh adjustment in memory devices configured for stacked arrangements

MEMORY MODULE INCLUDING BUFFER CHIP CONTROLLING REFRESH OPERATION OF MEMORY DEVICES

REFRESH SCHEME FOR MEMORY CELLS WITH WEAK RETENTION TIME

SEMICONDUCTOR MEMORY DEVICE AND DATA PROCESSING SYSTEM

Word shift static random access memory (WS-SRAM)

Memory and memory system including the same

Multi-processor computer architecture incorporating distributed multi-ported common memory modules

Semiconductor system and semiconductor package

Volatile memory device capable of relieving disturbances of adjacent memory cells and refresh method thereof

Multi-granularity parallel storage system

Information processing system including semiconductor device having self-refresh mode

Systems and methods for internal initialization of a nonvolatile memory

Reduction of power consumption in memory devices during refresh modes

Non-volatile memory interface

Electronic device with a power supply circuit for controlling the operations of a non-volatile memory and a volatile memory therein

INFORMATION PROCESSING SYSTEM INCLUDING SEMICONDUCTOR DEVICE HAVING SELF-REFRESH MODE

DRAM controller for variable refresh operation timing

Refresh control device, wireless receiver, and semiconductor integrated circuit

Memory devices and systems including multi-speed access of memory modules

Verifying shared memory integrity

Background auto-refresh apparatus and method for non-volatile memory array

Memory device refresh commands on the fly

Highly Efficient Design of Storage Array Utilizing Multiple Cache Lines for Use in First and Second Cache Spaces and Memory Subsystems

Dynamic random access memory with fully independent partial array refresh function

High-Speed Processor Core Comprising Mapped Auxilliary Component Functionality

Information processing system including semiconductor device having self-refresh mode

DRAM memory interface

Memory controlling device and method thereof for controlling memory with partial array self refresh (PASR) function

Memory systems and methods for dynamically phase adjusting a write strobe and data to account for receive-clock drift

Self-refresh control device and method for reducing a current requisite for self-refresh operation using the same

Methods and apparatuses for refreshing memory

Memory operations using system thermal sensor data

Apparatus and method for implementing a multi-level memory hierarchy