199534 ⎘
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency read-only digital stores using storage elements with more than two stable states
MEMORY DEVICE
#2ENCODED READ-ONLY MEMORY AND DECODER
#3MEMORY DEVICE
#4RADIATION HARDENED E-FUSE MACRO
#5Radiation hardened e-fuse macro
#6Non-volatile memory with multi-level cell array and associated read control method
#7Gradual breakdown memory cell having multiple different dielectrics
#8Multi-bit read-only memory device
#9Multi-bit-per-cell three-dimensional resistive random-access memory (3D-RRAM)
#10Bi-sided pattern processor
#11Dual-bit ROM cell with virtual ground line and programmable metal track
#12Double-biased three-dimensional one-time-programmable memory
#13Three-dimensional one-time-programmable memory with a dummy word line
#14Three-dimensional one-time-programmable memory comprising dummy bit lines
#15Multi-bit-per-cell three-dimensional one-time-programmable memory
#16Memory circuit and layout structure of a memory circuit
#17Estimating flash quality using selective error emphasis
#18Encryption engine with twin cell memory array
#19Dielectric-based memory cells having multi-level one-time programmable and bi-level rewriteable operating modes and methods of forming the same
#20Small-grain three-dimensional memory
#21Memory device, writing method, and reading method
#22Two-bit read-only memory cell
#23Three-dimensional nonvolatile memory and method of fabrication
#24N-bit rom cell
#25Low cost programmable multi-state device
#26Multi level antifuse memory device and method of operating the same
#27Pillar-shaped nonvolatile memory and method of fabrication
#28Small-grain three-dimensional memory
#29ANTIFUSE-BASED MEMORY CELLS HAVING MULTIPLE MEMORY STATES AND METHODS OF FORMING THE SAME
#30Semiconductor memory device
#31Programmable resistive memory unit with multiple cells to improve yield and reliability
#32Programmable resistive memory unit with data and reference cells
#33Multiple-state one-time programmable (OTP) memory to function as multi-time programmable (MTP) memory
#34Multiple-bit programmable resistive memory using diode as program selector
#35Vertically stacked field programmable nonvolatile memory and method of fabrication
#36Nonvolatile semiconductor storage
#37Multi-level electrical fuse using one programming device
#38Thermo programmable resistor based ROM
#39Read only memory device with complemenary bit line pair
#40Transistor having an adjustable gate resistance and semiconductor device comprising the same
#41Read-only memory (ROM) bitcell, array, and architecture
#42Encoded read-only memory (ROM) decoder
#43HIGH DENSITY AND LOW VARIABILITY READ ONLY MEMORY
#44Rewritable memory device with multi-level, write-once memory cells
#45Multi-valued ROM using carbon-nanotube and nanowire FET
#46Read only memory cell for storing a multiple bit value
#47Vertically stacked field programmable nonvolatile memory and method of fabrication
#48Circuit structure and method for programming and re-programming a low power, multiple states, electronic fuse (e-fuse)
#49ROM array with shared bit-lines
#50NROM memory cell, memory array, related devices and methods
#51Flash memory apparatus and methods using a plurality of decoding stages including optional use of concatenated BCH codes and/or designation of “first below” cells
#52Multilevel one-time programmable memory device
#53Integrated circuit incorporating decoders disposed beneath memory arrays
#54Programming a memory cell with a diode in series by applying reverse bias
#55Method of making a diode read/write memory cell in a programmed state
#56CONVENTIONALLY PRINTABLE NON-VOLATILE PASSIVE MEMORY ELEMENT AND METHOD OF MAKING THEREOF
#57ROM array with shared bit-lines
#58Multi-level anti-fuse and methods of operating and fabricating the same
#59Multi-bit memory device using multi-plug
#60Method of programming cross-point diode memory array
#61Large capacity one-time programmable memory cell using metal oxides
#62MULTIPLE ANTIFUSE MEMORY CELLS AND METHODS TO FORM, PROGRAM, AND SENSE THE SAME
#63NROM MEMORY CELL, MEMORY ARRAY, RELATED DEVICES AND METHODS
#64NROM memory cell, memory array, related devices and methods
#65High forward current diodes for reverse write 3D cell
#66Multibit ROM memory
#67Logic coding in an integrated circuit
#68Phase-change TaN resistor based triple-state/multi-state read only memory
#69Multi-level electrical fuse using one programming device
#70Phase-change TaN resistor based triple-state/multi-state read only memory
#71Method of operating multi-level cell
#72Semiconductor device having multi-bit nonvolatile memory cell and methods of fabricating the same
#73Implanted multi-bit NAND ROM
#74Vertically stacked field programmable nonvolatile memory and method of fabrication
#75Multi-valued logic/memory cells and methods thereof
#76Method for using a mixed-use memory array
#77Method for reading a multi-level passive element memory cell array
#78High bandwidth one time field-programmable memory
#79Non-volatile memory cell with embedded antifuse
#80Method of making non-volatile memory cell with embedded antifuse
#81Programming methods to increase window for reverse write 3D cell
#82Multilevel nonvolatile memory cell comprising a resistivity-switching oxide or nitride and an antifuse
#83Read-only memory using linear passive elements
#84Antifuse circuit and method for selectively programming thereof
#85MEMORY CELL COMPRISING A DIODE FABRICATED IN A LOW RESISTIVITY, PROGRAMMED STATE
#86Method of making a diode read/write memory cell in a programmed state
#87Memory cell comprising switchable semiconductor memory element with trimmable resistance
#88Multibit memory cell
#89Method for using a memory cell comprising switchable semiconductor memory element with trimmable resistance
#90Method for using a multi-use memory cell and memory array
#91Multi-use memory cell and memory array
#92Conventionally printable non-volatile passive memory element and method of making thereof
#93Phase-change TaN resistor based triple-state/multi-state read only memory
#94Memory cell with high-K antifuse for reverse bias programming
#95Antifuse circuit
#96High density memory array system
#97Variable breakdown characteristic diode
#98Semiconductor device including a memory element
#99Multi-state NROM device
#100Multiple-time electrical fuse programming circuit
#101Multi-state NROM device
#102Vertically stacked field programmable nonvolatile memory and method of fabrication
#103Vertically stacked field programmable nonvolatile memory and method of fabrication
#104NROM memory cell, memory array, related devices and methods
#105NROM memory cell, memory array, related devices and methods
#106NROM memory cell, memory array, related devices and methods
#107Three-state memory cell
#108NROM memory cell, memory array, related devices and methods
#109NROM memory cell, memory array, related devices and methods
#110NROM memory cell, memory array, related devices and methods
#111Semiconductor ROM device and manufacturing method thereof
#112Printable non-volatile passive memory element and method of making thereof
#113Semiconductor device having multi-bit nonvolatile memory cell and methods of fabricating the same
#114Multibit phase change memory device and method of driving the same
#115Method for reading an array of multi-bit ROM cells with each cell having bi-directional read
#116Method for manufacturing a multiple-bit-per-cell memory
#117One-time programmable memory device
#118Multiple-time programmable resistance circuit
#119Multi-bit ROM cell, for storing one of n>4 possible states and having bi-directional read, an array of such cells, and a method for making the array
#120Multi-layered memory cell structure
#121Method for reading ROM cell
#122Programmable resistor eraseless memory
#123Electronic memory with tri-level cell pair
#124Method for forming multi-level mask ROM cell and NAND multi-level mask ROM
#125High density ROM cell
#126Multi-state NROM device
#127Integrated circuit incorporating three-dimensional memory array with dual opposing decoder arrangement
#128Memory device and method for simultaneously programming and/or reading memory cells on different levels
#129Multibit ROM cell and method therefor
#130Method for manufacturing a programmable eraseless memory
#131Method for programming programmable eraseless memory
#132Multi-bit ROM cell, for storing on of N>4 possible states and having bi-directional read, an array of such cells
#133Programmable eraseless memory
#134Multi-bit ROM cell with bi-directional read and a method for making thereof
#135Array of multi-bit ROM cells with each cell having bi-directional read and a method for making the array
#136Memory cell with a read selection transistor and a program selection transistor
#137Content addressable dynamic random-access memory with parallel search functionality
#138Read only memory having multi-bit line bit cell
#139MLC OTP operation with diode behavior in ZnO RRAM devices for 3D memory