199556 ⎘
Digital stores characterised by the use of storage elements not covered by groups , , or using resistive RAM [RRAM] elements; Auxiliary circuits; Reading or sensing circuits or methods Read using potential difference applied between cell electrodes
MEMORY DEVICE
#2LOW RESISTANCE CROSSPOINT ARCHITECTURE
#3Apparatuses including multi-level memory cells and methods of operation of same
#4MULTIPLE MEMORY STATES DEVICE AND METHOD OF MAKING SAME
#5Two-terminal non-volatile memory cell for decoupled read and write operations
#6Apparatus and method for controlling gradual conductance change in synaptic element
#7Resistive memory
#8Polarity-written cell architectures for a memory device
#9Low resistance crosspoint architecture
#10Memory cells with asymmetrical electrode interfaces
#11Apparatuses and methods including memory and operation of same
#12Two memory cells sensed to determine one data value
#13Semiconductor device including variable resistance element
#14Two-terminal reversibly switchable memory device
#15Semiconductor device including variable resistance element
#16Low resistance crosspoint architecture
#17Tapered cell profile and fabrication
#18Electronic device and method of operating memory cell in the electronic device
#19Semiconductor memory device
#20Adjustment of read and write voltages using a space between threshold voltage distributions
#21RESISTIVE MEMORY DEVICE HAVING A CONDUCTIVE BARRIER LAYER
#22Apparatus and method for controlling gradual conductance change in synaptic element
#23Electronic device and method of operating memory cell in the electronic device
#24Operations on memory cells
#25Non-volatile memory device having a reading circuit operating at low voltage
#26Electronic device and operating method of electronic device
#27Memory cells with asymmetrical electrode interfaces
#28Tapered cell profile and fabrication
#29Methods of forming a phase change memory with vertical cross-point structure
#30Semiconductor storage device
#31Two-terminal reversibly switchable memory device
#32Polarity-written cell architectures for a memory device
#33Resistive memory device with scalable resistance to store weights
#34Multiple memory states device and method of making same
#35Memory cells with asymmetrical electrode interfaces
#36Resistive memory
#37Voltage-enhanced-feedback sense amplifier of resistive memory and operating method thereof
#38Resistance change device, manufacturing method for the same, and storage apparatus
#39Methods and apparatus for three-dimensional non-volatile memory
#40Circuit and layout for resistive random-access memory arrays
#41Circuit and layout for resistive random-access memory arrays having two bit lines per column
#42Resistive random-access memory array with reduced switching resistance variability
#43Resistive random-access memory array with reduced switching resistance variability
#44Tailoring current magnitude and duration during a programming pulse for a memory device
#45Operations on memory cells
#46Apparatuses and methods including memory and operation of same
#47Apparatuses including multi-level memory cells and methods of operation of same
#48Resistive memory device having ohmic contacts
#49Resistive memory device having a conductive barrier layer
#50Memory cells with asymmetrical electrode interfaces
#51Tapered cell profile and fabrication
#52Memory cell, memory cell array and operating method thereof
#53Two-terminal reversibly switchable memory device
#54Operations on memory cells
#55Three-terminal metastable symmetric zero-volt battery memristive device
#56Neural networks using cross-point array and pattern readout method thereof
#57Resistive memory device
#58Neural network circuit
#59Methods of forming a phase change memory with vertical cross-point structure
#60Multi-state phase change memory device with vertical cross-point structure
#61Method, system and device for testing correlated electron switch (CES) devices
#62Method and apparatus for adjusting demarcation voltages based on cycle count metrics
#63Resistance change memory device
#64Memory cell, memory cell array, memory device and operation method of memory cell array
#65Tailoring current magnitude and duration during a programming pulse for a memory device
#66Apparatuses and methods including memory and operation of same
#67Three-terminal metastable symmetric zero-volt battery memristive device
#68Three-terminal metastable symmetric zero-volt battery memristive device
#69Conductive hard mask for memory device formation
#70Method of storing and retrieving data for a resistive random access memory (RRAM) array with multi-memory cells per bit
#71Memory system
#72Memory system for controlling read voltage using cached data and operation method of the same
#73Single-readout high-density memristor crossbar
#74Conductive hard mask for memory device formation
#75Two-terminal reversibly switchable memory device
#76Methods of storing and retrieving information for RRAM with multi-cell memory bits
#77Resistive random access memory having multi-cell memory bits
#78Memristance feedback tuning
#79Apparatuses including multi-level memory cells and methods of operation of same
#80Reading circuit for resistive memory
#81Conductive hard mask for memory device formation
#82Resistance-change memory operating with read pulses of opposite polarity
#83Apparatuses and methods including memory and operation of same
#84Method, system and device for non-volatile memory device operation
#85PROTON RESISTIVE MEMORY DEVICES AND METHODS
#86Resistive random access memory device embedding tunnel insulating layer and memory array using the same and fabrication method thereof
#87Memory device
#88Memory device
#89Reading resistive random access memory based on leakage current
#90NONVOLATILE MEMORY DEVICE AND METHOD FOR DRIVING SAME
#91Silicon based nanoscale crossbar memory
#92Two-terminal reversibly switchable memory device
#93Nonvolatile semiconductor storage device having improved reading and writing speed characteristics
#94INTEGRATED CIRCUIT DEVICE
#95Integrated circuit device
#96Electronic device
#97Read and write methods for a resistance change non-volatile memory device
#98Silicon based nanoscale crossbar memory
#99Resistive random access memory device and manufacturing method thereof
#100Two-terminal reversibly switchable memory device
#101Method of storing and retrieving information for a resistive random access memory (RRAM) with multi-memory cells per bit
#102Non-volatile storage system biasing conditions for standby and first read
#103Method and apparatus for read measurement of a plurality of resistive memory cells
#104Determining cell-state in phase-change memory
#105Determining cell-state in phase-change memory
#106Combined memories in integrated circuits
#107Two Terminal Re Writeable Non Volatile Ion Transport Memory Device
#108Silicon based nanoscale crossbar memory
#109Combined memories in integrated circuits
#110Semiconductor memory device
#111Electronic device incorporating memristor made from metallic nanowire
#112Resistive memory devices, memory systems and methods of controlling input and output operations of the same
#113Reading threshold switching memory cells
#114Resistance variable memory device and system
#115Silicon based nanoscale crossbar memory
#116Multi-terminal reversibly switchable memory device
#117Two-Terminal Reversibly Switchable Memory Device
#118Combined memories in integrated circuits
#119Memory using mixed valence conductive oxides
#120Electronic device and method of operating memory cell in the electronic device
#121Adjustment of read and write voltages using a space between threshold voltage distributions
#122RRAM with plurality of 1TnR structures
#123Semiconductor memory device
#124Resistive processing unit weight reading via collection of differential current from first and second memory elements
#125Method, system and device for error correction in reading memory devices
#126Compensating for parasitic voltage drops in circuit arrays
#127Resistive memory element
#128Resistive non-volatile memory and a method for sensing a memory cell in a resistive non-volatile memory