199757 ⎘
Checking stores for correct operation ; Subsequent repair ; Testing stores during standby or offline operation; Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals; Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing; Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details Location of test circuitry on chip or wafer
MEMORY TEST CIRCUIT, MEMORY ARRAY, AND TESTING METHOD OF MEMORY ARRAY
#2ATPG testing method for latch based memories, for area reduction
#3Memory test circuit, memory array, and testing method of memory array
#4MEMORY MODULE WITH REDUCED ECC OVERHEAD AND MEMORY SYSTEM
#5METAL ISOLATION TESTING IN THE CONTEXT OF MEMORY CELLS
#6Testing method for packaged chip, testing system for packaged chip, computer device and storage medium
#7Semiconductor integrated circuit and memory system
#8ATPG testing method for latch based memories, for area reduction
#9ATPG testing method for latch based memories, for area reduction
#10Testing method, testing system, and testing apparatus for semiconductor chip
#11Chip testing apparatus and system with sharing test interface
#12Memory module with reduced ECC overhead and memory system
#13Test key structure
#14Multi-chip package and method of testing the same
#15Memory module with reduced ECC overhead and memory system
#16At-risk memory location identification and management
#17Nonvolatile memory device
#18Memory device and test operation method thereof
#19Nonvolatile memory device, method of operating nonvolatile memory device and storage device including the same
#20Structure and method for testing three-dimensional memory device
#21Metal isolation testing in the context of memory cells
#22Quick configurable universal register for a configurable integrated circuit die
#23Method of self-testing and reusing of reference cells in a memory architecture
#24Nonvolatile memory device, method of operating nonvolatile memory device and storage device including the same
#25Semiconductor device and system including the same
#26Test circuit block, variable resistance memory device including the same, and method of forming the variable resistance memory device
#27Peripheral logic circuits under DRAM memory arrays
#28Anti-hacking mechanisms for flash memory device
#29Memory device and manufacturing method therefor
#30Metal isolation testing in the context of memory cells
#31Structure and method for testing three-dimensional memory device
#32Built-in-self-test circuits and methods using pipeline registers
#33Semiconductor device
#34Retention minimum voltage determination techniques
#35Independently driving built-in self test circuitry over a range of operating conditions
#36Full address coverage during memory array built-in self-test with minimum transitions
#37Stack type semiconductor memory and semiconductor system using the same
#38E-fuse test device and semiconductor device including the same
#39Semiconductor packages and data storage devices including the same
#40Stacked semiconductor apparatus and semiconductor system capable of inputting signals through various paths
#41Data pattern generation for I/O testing of multilevel interfaces
#42Data pattern generation for I/O testing
#43Semiconductor apparatus
#44Test partitioning for a non-volatile memory
#45Built-in self-test method and structure
#46Fabrication and testing method for nonvolatile memory devices
#47Control scheme for 3D memory IC
#48Memory system with a layer comprising a dedicated redundancy area
#49Memory device and method for driving memory device
#50Embedded processor
#51Semiconductor device capable of suppressing a coupling effect of a test-disable transmission line
#52Embedded processor
#53Test partitioning for a non-volatile memory
#54Semiconductor integrated circuit device
#55Embedded processor
#56Semiconductor device including address signal generating protion and digital-to-analog converter
#57Semiconductor memory device
#58Semiconductor memory device capable of suppressing a coupling effect of a test-disable transmission line
#59Integrated Circuit, Memory Module, Method of Operating an Integrated Circuit, Method of Fabricating an Integrated Circuit, Computer Program Product, and Computing System
#60CIRCUIT MEASURING OPERATING SPEED AND RELATED SEMICONDUCTOR MEMORY DEVICE
#61Wafer level I/O test, repair and/or customization enabled by I/O layer
#62Integrated Semiconductor Memory with a Test Function and Method for Testing an Integrated Semiconductor Memory
#63Probe card and measuring method for semiconductor wafers
#64System and method for testing one or more dies on a semiconductor wafer
#65Wafer level I/O test and repair enabled by I/O layer
#66Area efficient memory architecture with decoder self test and debug capability
#67Semiconductor wafer and method for testing ferroelectric memory device
#68System and method for testing one or more dies on a semiconductor wafer
#69Contactless wafer level burn-in
#70Semiconductor apparatus
#71Methods for erasing bit cells in a high density data storage device
#72SEMICONDUCTOR EMBEDDED MEMORY DEVICES HAVING BIST CIRCUIT SITUATED UNDER THE BONDING PADS
#73Discrete tests for weak bits
#74Flexible I/O partition of multi-die memory solution